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single_cycle_16bit_computer
- This single cycle 16-bit computer with testbenches written in Verilog. It shows a result based on the instruction memory. I also included documents about the structure of the single cycle computer-This is single cycle 16-bit computer with testben
SinglecycleCPU
- 用Verilog实现一个简单的单周期CPU，并运行Quicksort程序以验证正确性。-This file is written in Verilog to achieve a single cycle processor. It can run in Quartus2.
MIPS1CYCLE
- MIPS single-cycle processor design in verilog.Instruction memory to the design and initialise it with your assembly code-a. Load the data stored in the X and Y locations of the data memory into the X and Y registers. b. Add the X and Y registers an
singlecircle_cpu
- 实现十一条指令的单周期处理器，运用Verilog语言，顺利执行，仿真正确。-To achieve single-cycle instruction processor XI, the use of Verilog language, the successful implementation of the simulation is correct.
F10-Single-Cycle-MIPS
- This a verilog code of single cycle mips-This is a verilog code of single cycle mips
mips
- 利用Verilog HDL硬件描述语言实现单周期MIPS_CPU设计。-Design of single-cycle MIPS_CPU
cpu
- 用Verilog语言编写的单周期cpu，实现的指令有 add,addu,addi,addiu,sub,subu,clo,clz,xori,nor,slt,slti,sltu,sltiu,blez,j.-Verilog languages ??with single-cycle cpu, implementation instructions are add, addu, addi, addiu, sub, subu, clo, clz, xori, nor, slt, slti, sltu,
SigCylCPU
- 单周期cpu的设计实现在VHDL中的verilog中实现。 -Design and implementation of single-cycle cpu in VHDL to implement the verilog.
single_cpu
- 单时钟CPU在XilinxISE 10.1的全代码，由Verilog语言描述-Single-cycle CPU in Verilog developed on XilinxISE 10.1
MIPS-processor-Verilog-code
- 原创，MIPS处理器Verilog源码，在FPGA实现单周期MIPS处理器，实现存储访问指令load word(lw)和store word(sw)，算术逻辑指令add、addi、sub、and、or和slt跳转指令branch equal(beq)和jump(j)-Original, achieves single-cycle MIPS processor MIPS processor Verilog source code, the FPGA, storage access instruct
091220111singalcpu
- 用verilog HDL语言或者VHDL语言来编写，实现单周期CPU的设计。能够完成以下十六条指定： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti
a
- mips single cycle verilog code for add,sub,bne,slt,lw,sw,xori instructions-mips single cycle verilog code for add,sub,bne,slt,lw,sw,xori instructions
SCMIPS
- 使用verilog代码描述了一种简单的单周期MIPS处理器实现，并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
SingleCycleCPU.zip
- A complete single cycle cpu written in verilog. (Including test modules),A complete single cycle cpu written in verilog. (Including test modules)
SC_CPU
- single cycle CPU element design with Verilog
singleCPU
- 用Verilog实现的单周期CPU,分别实现I型、R型、J型指令，并包含测试文件。可供参考。-With single-cycle CPU Verilog implementation, respectively, to achieve type I, R, J-type instruction, and includes test files. For reference.
time_test
- 利用10M的时钟，设计一个单周期形状的周期波形。这是用Verilog写的-Use 10M clock cycle design a single cycle waveform shape. This is written in Verilog
SingleCycle8bitProcessor
- Simple 8-bit Single Cycle Processor in Verilog HDL
CPU-master
- 单周期CPU的Verilog源码实现，基于Vivado(Single cycle CPU Verilog source code implementation, based on Vivado)
Single_cpu
- 单周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)