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bingzhuanchuan
- 这是一个用VHDL语言编写的并口转串口程序，在altera开发系统下验证通过，运用于开发板与计算机之间的通信，源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communicatio
myUART
- 这是我用Xilinx公司的sparten3开发板,ISE集成开发环境，用VHDL语言开发的串口全双工通信程序，供大家参考，共同学习。-This is the company I used the sparten3 Xilinx development boards, ISE Integrated Development Environment, Using VHDL development of the full-duplex serial communication program, for
异步串行口
- 一种基于VHDL语言的实现计算机串行通信的简洁设计
VHDL语言的UART串行接口芯片程序
- VHDL语言的UART串行接口芯片程序
uart.rar
- VHDL语言编写的全功能串口模块（包含DTR，RTS等管脚），在CPLD器件上测试通过,VHDL language, full-featured serial modules (including DTR, RTS pin, etc.), in the CPLD device test
SPI_verilog_vhdl.rar
- SPI串口的内核实现（分别使用verilog和vhdl语言描述的）,The core of the realization of SPI serial port (using Verilog and VHDL language descr iption of the)
uart
- 采用VHDL语言编写的串口驱动程序，已调试通过，能够实现同PC机的数据传输，可读性好，可移植性好-VHDL language using the serial driver has been debugged, to achieve the same PC, the data transmission, readable and portable
UART
- 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
FPGAuartdebug
- FPGA串口界面调试程序,用VHDL语言实现-FPGA serial debugger interface, using VHDL language implementation
VerilogHDL_code
- 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees
led
- 与串口通讯控制led（使用VHDL硬件描述语言，通过Altera QuartusII 开发）-Serial control and communications led (the use of VHDL hardware descr iption language, through the development of Altera QuartusII)
87361001Uart2
- VHDL语言编写的UART串口通讯,2400Hz的波特率时钟-VHDL language UART serial communication, 2400Hz clock of baud rate
UART2_vhdl
- 这是VHDL语言的uart串口驱动 感觉很难写的 但是这个可以移植的 比较好-This is the VHDL language serial uart driver feel it is very difficult but this can be written by transplantation is better huh
verilog
- 一个很好的关于verilog的PPT 第1章 EDA设计与Verilog HDL语言概述 第2章 Verilog HDL基础与开发平台操作指南 第3章 Verilog HDL程序结构 第4章 VERILOG HDL语言基本要素 第5章 面向综合的行为描述语句 第6章 面向验证和仿真的行为描述语句 第7章 系统任务和编译预处理语句 第8章 VERILOG HDL可综合设计的难点解析 第9章 高级逻辑设计思想与代码风格 第10章 可综合状态机开发实例 第1
uart
- vhdl语言的串口发送/接收模块，本人用在多个工程，很好用。-vhdl language of the serial transmit/receive module, I used a number of projects, very good use.
UART
- VHDL语言写的串口发送、接收程序，根据晶振和相应的波特率修改分频器就可以实现！-Written in VHDL serial send, receive, process, according to crystal and the corresponding baud rate divider changes can be achieved!
uart-(VHDL)
- 利用VHDL语言实现的UART串口通讯，以经过下载验证-the UART program with VHDL as develop language
FPGA_UART
- 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA
VHDL-uart
- 本程序应用VHDL语言，详细描述了RS232串口协议，包括发送，接收，波特率的产生，模块化编程，对于初学者尤为有宜！-The program in VHDL language, the detailed descr iption of the RS232 serial protocol, including sending, receiving, and baud rate generation, modular programming, especially for beginners sho
rs232
- 使用VHDL语言在vivado平台上编的串口通信的完整工程，并能用EGO1开发板成功验证(The complete project of serial communication is compiled on the vivado platform using VHDL language, and it can be successfully verified with the EGO1 development board.)