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RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
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完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
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Working RS232 controller running at 9600 Hz.
Consist of Transmitter and Receiver Module.
Tested in FPGA Spartan 3
Included files for testing at FPGA
- Scan4digit .vhd - to display at 7 sgement display
- D4to7 .vhd - Convert HEX decimal to
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这是关于PS2和rs232串口的代码，verilog的，是深入了解串口的好的学习实例。-good code about rs232 and ps2
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VHDL source code for Serial communication (RS232)
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RS232 reciver vhdl code for RS232 EIA232-RS232 reciver vhdl code for RS232 EIA232
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rs232串口基于VHDL的代码 很有用的 正确的 rs232串口基于VHDL的代码 很有用的 正确的-RS232 serial port based on VHDL code is very useful for the correct RS232 serial port based on VHDL code is very useful
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