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伪随机序列产生器-代进位反馈移位寄存器,verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
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8*8乘法器设计
伪随机序列发生器
PS2键盘设计
均为VHDL-8* 8 multiplier design of pseudo-random sequence generator are PS2 keyboard design VHDL
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伪随机序列发生器得VHDL语言源代码,已通过仿真。-Pseudo-random sequence generator may VHDL language source code, by simulation.
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一些有用的VHDL代码 包括伪随机序列发生器等-VHDL code, including some useful pseudo-random sequence generator, etc.
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伪随机序列发生器,即M序列发生器,VHDL语言完成,已仿真通过。-Pseudo-random sequence generator, VHDL language completed, through simulation.
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