搜索资源列表
axis_fifo
- VIVADO下使用verilog编码的axi fifo的简单使用，仿真通过，供初学者学习。-Use the following VIVADO verilog coding axi fifo simple to use, through simulation, for beginners to learn.
Privite_rom_32_20160519
- xilinxＦＰＧＡROM32*1原语的使用，vivado工程，含有仿真测试文件Testbench,添加地址寄存器，能够按址寻找你所存储的数据，仿真一目了然，对初学者甚好,verilog语言实现该功能。-xilinxFPGAROM32* 1 primitive use, vivado engineering, simulation test file containing Testbench, add an address register, Anzhi can find the data yo
PingPang_buffer_20160526
- 源码仿真 乒乓 缓存，实现数据流的传输，含有仿真测试文件，vivado工程。-Source simulation ping-pong cache data stream transmission, the file containing the simulation test, vivado project.
mdio
- 用VIVADO软件编写的，实现以太网芯片88E1510中的mdio控制模块代码，并且含有VIO仿真文件-Written in VIVADO software, the realization of the Ethernet chip 88 e1510 mdio control module of code, and contains the VIO simulation file
tiaozhi
- 基于verilog HDL的数字正交解调FPGA实现，仿真结果验证正确，IDE为vivado 2014- U57FA u4E8Everilog HDL u7684 u6570 u5B57 u6B63 u4EA4 u89E3 u8C03 u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u6B3 u786E uFF0CIDE u4E3Avivado 2014
jietiao
- 基于verilog HDL的数字正交（调制）FPGA实现，仿真结果验证正确。vivado 2014- U57FA u4E8Everilog HDL u7684 u6570 u5B57 u6B63 u4EA4 uFF08 u8C03 u5236 uFF09FPGA u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u6B63 u786E u3002vivado 2014
I2C_slaver_verison3.0
- I2C从机模块，包含testbench，平台是vivado,仿真测试通过。(I2C slave module, including testbench, the platform is vivado, simulation test passed.)
Vivado--设计流程指导手册-(含安装流程与仿真)
- vivado设计流程指导文件，里面包含有软件安装流程以及仿真流程(Vivado design flow guidance document, which contains software installation process and simulation process)
MCPU
- 多周期CPU的verilog代码，用vivado可以仿真出波形(multi-cycle CPU by verilog and using vivado to simulate.)
sim_Xilinx综合与仿真设计指导
- Xilinx自己出的仿真设计指导，使用vivado工具必备参考资料。(The Synthesis and Simulation Design Guide provides a general overview of designing Field Programmable Gate Array devices using a Hardware Descr iption language. It includes design hints for the novice HDL user, as w
1_FM_Radio
- 基于vivado与MATLAB联合仿真,实现FM立体声广播，通过simulink的仿真以及Dps平台的帮助，可以直接下板运行(simulation basing on vivadao and matlab)
Sdram
- 在vivado中调用SDRAM的IP核，并通过数据的读入，读出，验证IP核的使用，文件中有仿真结果时序图。(In the vivado call SDRAM IP core, and read through the data, read, verify the use of IP kernel, the file has simulation results sequence diagram.)
Verilog HDL使用中该注意的问题及一些模块代码
- cpu仿真，提供vivado上的cpu仿真生成文件(cpu simulated,but no one can get 20 words in this short file how can I do? just tell you the simulated file and vivado system is 2015)
demodulation
- 基于verilog HDL的BPSK解调的FPGA实现，仿真结果验证良好。IDE为vivado 2014( U57FA u4E8Everilog HDL u7684BPSK u89E3 u8C03 u7684FPGA u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u826F u597D u3002IDE u4E3Avivado 2014)
VHDLcounter
- VHDL，四位counter，用Vivado写的，可运行，可模拟，可仿真，可写入硬件里，四个指示灯会每一秒闪一次。