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leon2-1.0.30-xst.tar
- Leon2 CPU VHDL Source Code 欧洲航天局资助开发的LEON CPU,源码遵循GPL -Leon2 CPU VHDL Source Code European Space Agency funded the development of LEON CPU, followed source GPL
jamcpu
- jam CPU模拟器的设计与实现.其中包含设计文档-jam CPU Simulator Design and Implementation. which includes design documents
uart
- 用ALTERA的芯片做的多串口代码，内部做了3个通用串口，适合51 ARM等CPU，有完整的ALTERA工程和仿真波形-uart FOR ALTERA
pipeline
- 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
cup
- cpu控制器用vhdl代码编写组成原理的控制器组合逻辑-cpu controller using vhdl coding theory composed of combinational logic controller
16-bit_cpu_design
- 详细介绍了如何设计一个简单的16位cpu.其中包含了从最基础的指令系统开始到最复杂的cu控制器的设计思路，方案.最后还介绍了一些有关vhdl语言的用法,并给出了具体的cpu部件的vhdl代码,从而帮助大家更为深刻的学习如何设计一个简单的cpu-Described in detail how to design a simple 16-bit cpu. Which contains the most basic instruction from the beginning to the most
cpu
- 基于十二条简单汇编指令构成的一个cpu 采用vhdl语言编写 内附源代码 工具sylinx-Based on 12 simple assembly instructions consisting of a cpu using vhdl language source code tool sylinx included
cpu
- 16位的5级流水线cpu 采用vhdl代码 modelsim编译仿真-5-stage pipeline 16-bit cpu compiled simulation using modelsim vhdl code
scpu
- 一些零散而简单的CPU功能部件，一部分源码是放在TXT文件中，只要改成VHDL格式就可以使用。-Some scattered and simple CPU features, part of the source is placed in TXT file into VHDL format as long as you can use.
VHDL-cpu
- 根据计算机组成原理课程所学的知识和本课程所讲的设计思想，设计一个给定指令系统的处理器，包括：VHDL语言的实现；FPFA芯片的编程实现； -Based on the knowledge and the curriculum computer architecture course learn about design thinking, design a given the instruction system' s processor, including: the realizat
vhdl
- vhdl cpu芯片逻辑设计的一部分实现 只有一小部分 大家可以看一下 寄存器 加法器之类的-vhdl cpu chip logic design part of its implementation only a little part everry look and see b=about registers adder and so on
cpu
- 《vhdl编程实例》（第四版）内的cup设计源代码 -Cup design source code " vhdl programming examples" (fourth edition)
CPU
- 在THINPAD平台上的50M时钟5级流水支持THCOMIPS指令集的CPU，并附带8核扩展，内有详细实验报告。全部用VHDL编写，并附有样例验证程序，开发环境为ISE 14.1。-Water support THCOMIPS instruction set CPU 50M clock the THINPAD platform 5 and comes with an 8-core extension, within a detailed test report. All written usin
intheend
- VHDL设计CPU完整版的VHDL实验程序和下载到实验台上的程序 可能有一些小的错误需要自己调整一下 包括取值、运算、存出、写回和控制几大模块-The full version of the VHDL design CPU VHDL experimental procedures and downloaded to the experimental stage, the program may have some small errors need to adjust the values, c
CPU_VHDL
- 这是实现一个8位和16位cpu的VHDL代码，虽然支持的指令比较少只有20多条，但对于学习CPU的布线架构很有帮助-This is achieved by an 8-bit and 16-bit cpu VHDL code, although only a relatively small instruction support more than 20, but for learning routing architecture CPU helpful
CPU
- 简单的CPU设计,使用VHDL 和 quartus ii 设计的cpu(a simply cpu design, vhdl quartus ii ,dsg gs h srh rsh rsh srjh srh)
lu
- 16位MIPS指令集，VHDL实现，非常简单，非常粗暴(library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;)