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embedded_risc
- 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
minirisc
- minirisc Mini-RISC CPU-Microcontroller that is compatible with the PIC 16C57 from Microchip Mini-RISC CPU-Microcontroller ＩＰ核 -minirisc Mini-bit RISC CPU-Microcontroller that is compatible with the PIC 16C57 from Micro chip Mini-bit RISC CPU-Micr
RISC_Core.ZIP
- 这是一篇关于8位RISC CPU设计的文章，其中包含了用Verilog语言编写的CPU内核程序
ethernet_verilog
- 这是一个很好的Verilog 编写的8位RISC CPU源码（可做为MCU），并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
处理器
- 16-bit RISC CPU
S3C2440_H324
- 在现有的PSTN 网络上构建了一个嵌入式终端平台,该平台基于RISC 架构ARM 处理器S3C2440A,符合国际电联ITUT 建议的H.324 协议。此系统平台在原有的MCU+DSP 的架构基础上提出一种纯基于RISC 架构的ARM 处理器的可视电话 平台,该方案更加灵活, 可以用于现有的办公,家庭等环境.-Build a embedded platform of the ARM920T core RISC CPU S3C2440, which can connected to PST
32-bit-RISC-CPU-ARM
- 32位RISC CPU ARM芯片的应用和选型-32-bit RISC CPU ARM chip application and selection
RISC-CPU-ARM
- 32位RISC CPU ARM芯片的应用和选型-32-bit RISC CPU ARM chip application and selection
BuildingPaPRISCPSystemPinPanPFPGA
- 一个32位 RISC CPU 核心，由Verilog 编写而成-A 32-bit RISC CPU core, written by Verilog
CPU_test
- 设计并通过modelsim仿真软件实现了一个可以在FPGA平台上运行的8位RISC的CPU软核-Design an 8-bit RISC CPU soft core on an FPGA platform and simulate it using ModelSim
RISC_CPU
- 本例子是一个精简指令集CPU，非常好用经过测试-This example is a RISC CPU, very handy tested