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Simple_digital_circuit_design
- 简单的数字电路设计，全部由分立的IC实现，实物已经做出过。实现两个四位二进制数相加，和一个四位二进制移位的功能。仿照MCU指令进行设计，有2位二进制操作码，8位输入和5位输出端，内部时钟控制电路。对于了解8位或者16位的MCU指令时序逻辑有点帮助.-Simple digital circuit design, all of the IC to achieve the separation, in-kind has been made. The achievement of the two add
shuzhiluoj
- 把时序逻辑电路设计和组合逻辑电路设计相结合，设计一个有实际应用的数字逻辑电路余3码转换成2421 BCD 码-The sequential logic circuit design and the design of combinational logic circuit by combining the design of a practical application of digital logic circuits into three yards more than 2421 BCD
Static_timing_analysis_and_logic_design
- 本文主要对硬件电路的静态时序分析与逻辑设计，概念，工具使用等方法进行介绍说明-In this paper, the hardware circuits static timing analysis and logic design, concepts, tools and methods of use of an introductory statement
main
- 数字钟是一种用数字电路技术实现时、分、秒计时的装置，与机械式时钟相比具有更高的准确性和直观性，且无机械装置，具有更更长的使用寿命，因此得到了广泛的使用。数字钟从原理上讲是一种典型的数字电路，其中包括了组合逻辑电路和时序电路。目前，数字钟的功能越来越强，并且有多种专门的大规模集成电路可供选择-Digital Clock is a digital circuit technology with the hours, minutes, seconds, timing devices, as compa
Classical_sequential_logic_circuits_tutorial
- 时序逻辑电路经典教程Classical sequential logic circuits tutorial-Classical sequential logic circuits tutorial Classical sequential logic circuits tutorial
Sequential_logic_circuit_analysis_and_design_metho
- 时序逻辑电路的分析方法和设计方法Sequential logic circuit analysis and design methods-Sequential logic circuit analysis and design methods Sequential logic circuit analysis and design methods
The-temporal-logic-circuit-design
- 时序逻辑电路设计 实验内容 1．触发器（Ｄ型）； 2．计数器（递增、递减）。-Sequential logic circuit design, the contents of an experiment. Flip-flop (D type) 2. Counter (increasing, decreasing).
eda
- 在Verilog HDL中使用任务（task）， 利用有限状态机进行时序逻辑的设计，利用SRAM设计一个LIFO(In Verilog HDL, the task (task) is used, the finite state machine is used to design the time series logic, and a LIFO is designed by SRAM)