搜索资源列表
pwm
- pwm的占空比和死区时间可调的Verilog HDL程序设计和测试-duty cycle of pwm and adjustable dead time of the Verilog HDL design and testing procedures
hex2led
- 在quantusII环境下采用verilog HDL语言编辑的7段译码器HEX2LED设计 -In quantusII environment using verilog HDL language editors design 7-segment decoder HEX2LED
counter
- 计数器是数字电路系统中最基本的功能模块之一，设计时可以采用原理图或HDL语言完成。 下载验证时的计数时钟可选用连续或单脉冲，并用数码管显示计数值。 -The counter is one of the basic function module in the digital circuit system, can be used in the design of the schematic or HDL language completed. The download validatio
FPGA-design-and-verification-using-Simulink
- Xilinx System Generator for DSP is a MATLAB Simulink block set that facilitates system design. Targeting Xilinx FPGAs within the familiar MATLAB environment, System Generator for DSP gives you the ability to functionally simulate a design and use
eda
- 在Verilog HDL中使用任务（task）， 利用有限状态机进行时序逻辑的设计，利用SRAM设计一个LIFO(In Verilog HDL, the task (task) is used, the finite state machine is used to design the time series logic, and a LIFO is designed by SRAM)