The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia p

以FPGA为核心，实现正弦波、调制波AM、FM、ASK和PSK等功能，通过SPI协议与STM32通信，实现输出波形的选择、频率的设置和基带信号的设定等。(With FPGA as the core, the functions of sine wave, modulation wave AM.FM. ASK and PSK are realized. The output waveform selection, frequency setting and baseband signal sett