七段数码管显示程序，用Verilog语言编写，程序运行完全没有问题。,Seven-Segment LED display program, with the Verilog language, the program is running is no problem.

Verilog HDL源码，显示器段数码管数字累加，测试通过-Verilog HDL source code, the display segment digital tube digital cumulative, testing through

Abstract七段显示器在DE2可当成Verilog的console，做为16进位的输出结果。Introduction使用环境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)简单的使用switch当成2进位输入，并用8位数的七段显示器显示16进位的结果。-Abstract Seven-Segment Display as Verilog to DE2 at the console, as 16 of the output binary. In

在quantusII环境下采用verilog HDL语言编辑的7段译码器HEX2LED设计 -In quantusII environment using verilog HDL language editors design 7-segment decoder HEX2LED