搜索资源列表
filter 代码
- 用verilog实现滤波器的功能，通过软件综合仿真，在利用FPGA实现-using Verilog filter function to achieve through integrated simulation software, the use of FPGA
color_converter.tar
- 此代码实现不同图像颜色制式之间的相互转换，如XYZ<->RGB, 不同标准的RGB<->RGB 以及RGB<->YCbCr之间的转换，包内含有matlab仿真代码m文件、VHDL代码.v文件以及modelsim仿真的testbench文件，相信对大家有一定的帮助
dds正弦发生器代码
- 讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for sim
sdram 仿真模型
- sdram 仿真模型,用于verilog代码sdram行为级仿真-sdram modelsim model
SDR
- 直接序列扩频通信的Verilog仿真代码，在Quartus II中实现。-Direct sequence spread spectrum communication Verilog simulation code, implemented in Quartus II.
crc
- 自己写的循环冗余校验，进行了仿真，整个工程都在！-Wrote it myself, cyclic redundancy check carried out a simulation, the whole project are in!
sdram_vhd
- FPGA设计的SDRAM控制器，有仿真代码，已通过验证-FPGA Design of SDRAM controller, there is simulation code has been validated
FIR
- FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。-FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.
VHDL_for_clock
- 基于VHDL语言的数字钟设计，附有完整的程序代码，并有仿真结果。-VHDL-based digital clock design, with a complete code, and have the simulation results.
sipo8
- 串入并出源代码，可进行8位数据的串/并转换。其中包括QUARTUS2的完整工程，有正确的仿真波形供参考。-In series and the source code, can be 8-bit data series/parallel conversion. Including QUARTUS2 complete project,and the correct simulation waveform for reference.
mux
- 本例实现的功能是一个16位的乘法器，并增加了仿真代码-In this case the function is to achieve a 16-bit multiplier, and to increase the simulation code
I2C_Verilog_Model
- 该源程序包是I2C的Verilog语言模型，包括以下4个部分：RTL源代码，测试平台，软件仿真代码，说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
compare.v
- compare比较器设计程序源码及仿真代码，下载可用-Comparison of design and simulation program source code, available for download
1024Mb_ddr2
- DDR2的Verilog仿真代码，可以使用ModelSim仿真-DDR2' s Verilog simulation code, you can use the ModelSim simulation
vga_modelsim
- 这是一个通过modelsim仿真通过的例子，学会如何仿真代码，程序思路清晰明了，易学习。-This is a adopted by the modelsim simulation examples, learn how simulation code, program ideas clarity, easy to learn.
target_6
- 通过设计信号延迟的，目标模拟器设计，包括源代码，仿真代码，以及仿真结果图-Through the design of signal delay , the target simulator design , including the source code , simulation code and simulation results in Figure
pc_cfr_v3_0_msim
- xilinx pc-cfr仿真代码,供参考-xilinx pc cfr matlab code ,for reference
scr
- 60进制计数器同步置位30异步复位 modelsim仿真代码含激励 自己写的 可用 仅供参考入门-60 binary counter 30 the asynchronous reset modelsim simulation code containing motivate yourself to write synchronization set can be used for reference only entry
vga
- 此例程为基于FPGAVGA/LCD显示控制的实例，用Verilog语言实现。代码中有详细注释。并有相应的仿真代码，可以验证其功能完整性。-This routine for the FPGAVGA/LCD display control based on examples, using Verilog language. The code has detailed notes. And a simulation code corresponding, can verify its function
Matlab
- 基于数字基带传输系统MATLAB仿真代码，以及相关文件。-Based on the digital baseband transmission system MATLAB simulation code, and related documents.