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VHDL_Development_Board_Sources
- 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code q
verlog_basic
- 用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器，乘法器，除法器，多路选择器，二进制转BCD码，加法器，减法器等等。-verlog used some language addendum to the basic experiment, which is suitable for FPGA / CPLD beginners. Including eight priority encoder, multipliers, dividers, multi-p
用assign 语句描述的三态门
- 用assign 语句描述的三态门，三态双向驱动器，3-8 译码器，8-3 优先编码器等等,With the assign statement describing the three-state gate, three-state bi-directional drive, 3-8 decoder ,8-3 priority encoder, etc.
encode
- 8位优先编码器。 8位优先编码器。-8-bit priority encoder. 8-bit priority encoder. 8-bit priority encoder.
8ENCODE
- 8位优先编码器 verilog CPLD EPM1270 源代码-8-bit priority encoder verilog CPLDEPM1270 source code
decoder_3_8
- 采用VHDL语言编写8线-3线优先编码器，在MAX+plus软件下实现。-Using VHDL language-3 line 8 line priority encoder, in MAX+ Plus software to achieve.
2
- 里面有四个vhdl源程序 分别为状态机 三位表决器 和交通灯 优先编码器-There are four VHDL source code for the state machine, respectively, the three voting machines and traffic lights priority encoder
vhdlexperiences
- 计数器、频率计、优先编码器、数码管扫描电路、数据选择器-Counter, frequency meter, priority encoder, digital tube scanning circuits, data selector
Mars-EP1C6-F_code1
- 此包中为FPGA学习板中的基础实验代码.共包括8个实验源代码:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机和四位比较器.-In this package for the FPGA board to study the basis of the experiment code. A total of eight experiments, including source code: 8-bit priority encoder, multipliers, mul
irq_decoder
- 中断优先编码器的描述，输出中断向量供CPU读取，非常好用，只要稍稍修改，就可以产生您所需要的中断向量。-Descr iption of interrupt priority encoder, the output for the CPU interrupt vector read, very easy to use, if slightly modified, it can generate interrupt vector you need.
6_coder
- VHDL编写！8-3线编码器大全！ 包括 coder8_3.vhd 8线/3线编码器 coder8_3_1.vhd 8线/3线编码器 sn74ls148.vhd 8线/3线优先编码器 coder16_4.vhd 16线/4线优先编码器-VHDL write! 8-3 line encoder Daquan! Including coder8_3.vhd 8 line/3 line encoder coder8_3_1.vhd 8 line/3 line encoder sn7
answermachine5
- 这次设计的抢答器主要四部分组成，由优先编码器，寄存器和译码器组成的抢答电路，十进制计数器组成的倒计时电路，555定时器组成的秒脉冲发生器，十六进制计数器组成的计数器。-The design of the Responder mainly of four parts, by the priority encoder, register, and the composition of the answer in the decoder circuit, consisting of decimal c
74LS148
- 用vhdl语言编译一个优先编码器74LS148-vhdl 74LS148 code
VHDL
- EDA技术以EDA软件工具为开发环境，以可编程逻辑器件为实验载体，实现源代码编程和仿真功能。VHDL作为一种标准化的硬件描述语言用于描述数字系统的结构、行为、功能和接口。本设计提出了一种基于VHDL语言的编码器和译码器的实现方法。编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。编码器由8线-3线优先编码器作为实例代表，译码器则包含3线-8线译码器和2线-4线译码器两个实例模块组成。课程设计采用硬件描述语言VHDL把电路按模块化方式进行设计，然后进行编程、时序仿
exp1.2_priencoder8_3
- 用VHDL及verylog语言设计一个8_3优先编码器，可以在Quartus II中仿真-Language Design with VHDL and verylog a 8_3 priority encoder, the Quartus II simulation in
Eight-priority-encoder
- 八位的优先编码器 具有优先编码的功能 程序简单易懂-Eight priority encoder
83
- 基于FPGA的83优先编码器源代码，赛林思比赛专用-Based on FPGA 83 priority encoder the source code, and the "special LinSi game
CODER
- 基于FPGA的8线-3线优先编码器的设计，QuartusII编译通过，采用VHDL语言编写。-Based on FPGA eight line-3 line is preferred encoder design, QuartusII compile, USES the VHDL language.
encoder
- 八位优先编码器，是用FPGA写的代码，使用ALTERA 飓风处理器，代码运行速度比较快，验证没有错误-Eight priority encoder, write code using FPGA using ALTERA hurricane processor, code runs faster, verify that no errors