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Pall_FIR
- FIR低通滤波器得设计，采用并行算法设计
09
- 应用分布式算法在FPGA平台实现FIR低通滤波器
LowpassfilterVHDLcord
- 低通滤波器的VHDL代码，需要的可以下来看看，本人QQ147440013，有志同道合的人可以加我哦
fir_16
- fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz
FIR低通滤波器部分模块
- 一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with -30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
filter_verilog.rar
- 用verilog实现的低通滤波器，输入输出精度为64位，并附有测试程序。,Use verilog to achieve a low-pass filter, input and output accuracy of 64, together with testing procedures.
filter
- 如何利用verilog设计数字滤波器 包含低通滤波器,带通滤波器,高通滤波器.-how to design a digit filter with Verilog
FIR
- Quartus II中滤波器的设计，里面含有高通滤波器，低通滤波器，带阻滤波器，主要用于滤除心电信号中的干扰-Quartus II filter design, which contains a high-pass filter, low-pass filter, band stop filter, mainly used for filtering of ECG signal interference
fir
- verilogHDL编写的低通滤波器模块，在ISE软件中仿真过-verilogHDL prepared by low-pass filter module, in the ISE simulation software have been
rmfilter
- 低通滤波器在QUARTUS7.0开发环境下的文本与框图结合的实现方法的源代码-Low-pass filter QUARTUS7.0 development environment in the text and diagram combination of methods to achieve source code
TheDesignofFIRFilterBasedonFPGA
- 从分析FIR 数字滤波器的原理和设计方法入手,主要针对基于FPGA 实现数字滤波器乘法器的算法进行了比较研究,并通过一个8 阶FIR 低通滤波器的具体设计,简要分析比较了几种算法的优越性和缺点,从而充分发掘和利用FPGA 的高速特性。-From the analysis of FIR digital filter design theory and approach, mainly based on the realization of digital filter FPGA multiplie
firfilter
- FIR滤波器：自定滤波器的类型（低通，高通或带通）、设计指标（通带截止频率、通带波纹、阻带截止频率、阻带衰减） 1、根据指标选择合适的窗函数，用窗口设计法设计符合指标的FIR滤波器；并验证其性能是否满足预定指标。 -FIR filters: Custom filter types (low pass, high pass or band-pass), design specifications (passband cutoff frequency, passband ripple, st
fir_filter
- 采用vhdl语言在Altera的开发板DE2-70上实现的低通滤波器的工程-Vhdl language used in the Altera DE2-70 development board to achieve the low-pass filter project
224
- 直接数字合成器中贝塞尔低通滤波器设计。非常适应-Direct digital synthesizer Bessel low-pass filter design. Is to adapt
FirAlgs
- 本代码用C语言实现了有限冲击响应低通滤波器的设计。-The code used C language to implement low-pass finite impulse response filter design.
FIR_Filter
- verilog的32阶FIR低通滤波器描述-verilog 32-order FIR low-pass filter described
fir
- 基于verilog的 FIR低通滤波器的实现(Implementation of FIR low pass filter based on Verilog)
fir
- fir 滤波器的程序文件和测试文件，仿真数据和matlab仿真数据进行过比对，matlab采用fdatool生成的低通滤波器，采样率为24兆，通带2.5M，截止频率为5M(FIR filter program files and test files, simulation data and MATLAB simulation data have been compared, Matlab using FDATool generated low-pass filter, sampling rat
scripts
- 低通滤波器的实现，通过不同的切割方式实现后，生成的vivado文件资源的使用情况不同，对其进行分析(The implementation of the low pass filter, after the implementation of different cutting methods, the use of the generated vivado file resources is different, to analyze it.)
滤波器实验报告
- 设计一个 1MHz 的 FIR 低通滤波器。 要求： ① 时钟信号频率 16MHz; ② 输入信号位宽 8bits，符号速率 16MHz ③ 要求在 Matlab 软件中进行 FIR 滤波器浮点和定点仿真，并确定 FIR 滤波器抽头系数 ④ 写出测试仿真程序。(Design a 1MHz FIR low pass filter. Requirements: (1) clock signal frequency 16MHz; (2) input signal bit width