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Pall_FIR
- FIR低通滤波器得设计，采用并行算法设计
09
- 应用分布式算法在FPGA平台实现FIR低通滤波器
fir_16
- fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz
FIR低通滤波器部分模块
- 一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with -30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
FIR
- Quartus II中滤波器的设计，里面含有高通滤波器，低通滤波器，带阻滤波器，主要用于滤除心电信号中的干扰-Quartus II filter design, which contains a high-pass filter, low-pass filter, band stop filter, mainly used for filtering of ECG signal interference
fir
- verilogHDL编写的低通滤波器模块，在ISE软件中仿真过-verilogHDL prepared by low-pass filter module, in the ISE simulation software have been
TheDesignofFIRFilterBasedonFPGA
- 从分析FIR 数字滤波器的原理和设计方法入手,主要针对基于FPGA 实现数字滤波器乘法器的算法进行了比较研究,并通过一个8 阶FIR 低通滤波器的具体设计,简要分析比较了几种算法的优越性和缺点,从而充分发掘和利用FPGA 的高速特性。-From the analysis of FIR digital filter design theory and approach, mainly based on the realization of digital filter FPGA multiplie
firfilter
- FIR滤波器：自定滤波器的类型（低通，高通或带通）、设计指标（通带截止频率、通带波纹、阻带截止频率、阻带衰减） 1、根据指标选择合适的窗函数，用窗口设计法设计符合指标的FIR滤波器；并验证其性能是否满足预定指标。 -FIR filters: Custom filter types (low pass, high pass or band-pass), design specifications (passband cutoff frequency, passband ripple, st
vhdl_fir
- 1、输入输出数据宽度为12位， 2、阶数为4阶段线性相位FIR滤波器， 3、类型为：低通。 -1, input and output data width is 12, 2, 4 stages of the order of linear phase FIR filter, 3, type: low pass.
FIR_128
- FIR 128阶低通滤波器，由matlab仿真并在quartusII中实现-FIR 128 order low-pass filter
FIR_matlab_verilog
- matlab 仿真低通滤波器，然后用verilog硬件实现-using matlab to simulate a fir lowpass, then using verilog to implement it.
FIR_Filter
- verilog的32阶FIR低通滤波器描述-verilog 32-order FIR low-pass filter described
FIR_lowpass_part
- 实现FIR滤波器的并行算法，这里是一个64阶的低通滤波器-FIR filter of parallel algorithm
fir_lowpass
- 硬件语言实现数字低通滤波器，使用ise11.1和modelsim se6.5 仿真测试-Hardware language digital low pass filter, the use of simulation testing ise11.1 and modelsim se6.5
fir
- 用Verilog语言设计的一个数字FIR低通滤波器，很实用，通过modelsim仿真成功-Verilog language to design a digital FIR low-pass filter, very practical, through modelsim simulation success
fir
- 基于FPGA的低通滤波器的设计，仿真环境是QuartusII9.0。对信号进行低通滤波，编程成功。希望对大家有所帮助-FPGA-based low-pass filter design, the simulation environment QuartusII9.0. The signal is low-pass filtering, the programming was successful. We hope to help
fir-digital--lowpass-filter
- 基于verilogHDL硬件描述语言的fir数字低通滤波器的设计-fir digital lowpass filter design based on verilogHDL
fir
- 基于verilog的 FIR低通滤波器的实现(Implementation of FIR low pass filter based on Verilog)
fir
- fir 滤波器的程序文件和测试文件，仿真数据和matlab仿真数据进行过比对，matlab采用fdatool生成的低通滤波器，采样率为24兆，通带2.5M，截止频率为5M(FIR filter program files and test files, simulation data and MATLAB simulation data have been compared, Matlab using FDATool generated low-pass filter, sampling rat
滤波器实验报告
- 设计一个 1MHz 的 FIR 低通滤波器。 要求： ① 时钟信号频率 16MHz; ② 输入信号位宽 8bits，符号速率 16MHz ③ 要求在 Matlab 软件中进行 FIR 滤波器浮点和定点仿真，并确定 FIR 滤波器抽头系数 ④ 写出测试仿真程序。(Design a 1MHz FIR low pass filter. Requirements: (1) clock signal frequency 16MHz; (2) input signal bit width