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基于FPGA的直接数字合成器设计
- 1、 利用FLEX10的片内RAM资源，根据DDS原理，设计产生正弦信号的各功能模块和顶层原理图； 2、 利用实验板上的TLC7259转换器，将1中得到的正弦信号，通过D/A转换，通过ME5534滤波后在示波器上观察； 3、 输出波形要求： 在输入时钟频率为16KHz时，输出正弦波分辨率达到1Hz； 在输入时钟频率为4MHz时，输出正弦波分辨率达到256Hz； 4、 通过RS232C通信，实现FPGA和PC机之间串行通信，从而实现用PC机改变频率控制字，实现对输出正弦波频率的控制。-a use
AD9833
- VHDL语言 状态机实现AD9833信号的产生-VHDL language state machine to achieve AD9833 signal generation
test_ad9852
- 使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。使用的DDS芯片为AD9852，在QuartusII下编写。-Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.
singnal
- VHDL实现通用通信信号源，包括sin，cos，方波，三角波，BPSK，GMSK，ASK，16QAM等信号的产生以及DDS，PLL的VHDL系统代码-VHDL implementation of universal communication sources, including sin, cos, square, triangle, BPSK, GMSK, ASK, 16QAM and other signal generation and DDS, PLL system, the VHDL
dds
- 实现数字频率合成。能产生任意频率的正弦信号、方波信号、梯形波等，并且能对信号的频率进行测量。-Digital frequency synthesizer. Can generate any frequency sinusoidal signal, square-wave signal, a trapezoidal wave, etc., and can measure the frequency of the signal.
FPGA_DDS
- 基于Cyclone EP1C6240C8 的AD9854 DDS的接口程序，使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。 通过FPGA口线模拟AD9854的控制时序。 提供DDS信号波形变换、DDS频率调整、DDS内部比较器使用等功能。-Cyclone EP1C6240C8 of the AD9854 DDS-based interface program, use the FPGA to control the DDS signal generation, so a
timebase
- 实现了时基信号的产生，频率50MHz,在SPARTAN-3E板子上用。-Time-based signal，which developed on board SPARTAN-3E of xilinx.
VGA
- 使用VHDL语言和FPGA器件实现VGA彩条信号的产生。-Using the VHDL language and FPGA devices to achieve VGA color bar signal generation.
ALUandControl
- 用verilogHDL编写的ALU功能实现以及控制信号的产生，还附有波形仿真测试的源文件-Written by verilogHDL ALU function realization and control signal generation, but also with a simulation test of the source waveform
triangle_LFM
- DDS芯片产生三角波线性调频信号的FPGA程序-DDS chip generated triangular wave linear FM signal of the FPGA program
SIN_NEW1Hz
- 正弦波信号的产生,频率为1Hz,FPGA处理模块各部分所需工作时钟信号由输入系统时钟信号经分频得到，系统时钟输入端应满足输入脉冲信号的要求-generte sin wave, the frequence is 1Hz,FPGA processing module is required to work various parts of the system clock signal from the input clock signal by dividing the system clock
pwm
- 利用verilog来实现PWM信号的产生-PWM verilog
square-generator
- 本文描述了怎样进行方波信号的产生，步骤，还有相关的程序-this paper describe how to generate square wave
NIOSII_TFT
- 基于FPGA的NIOSII_TFT做的做的正弦波很连贯的显示在液晶屏上面，FPGA主要做信号的产生，而NIOSII主要是驱动液晶画活出波形！-FPGA-based NIOSII_TFT do make a very coherent sine wave displayed on the LCD screen above, FPGA mainly to do signal generation, while NIOSII mainly driven liquid crystal painting
randomization
- 伪随机序列应用设计:利用verilog代码实现伪随机信号的产生-Pseudo-random sequence application design: the use of pseudo-random signals verilog code generation
1
- 信号发生器VHDL实现,实现一种信号的产生-Signal generator VHDL implementation to achieve produce a signal
CORDIC_IP
- 基于CORDIC实现正弦信号的仿真实验，通过使用自带的IP核CORDIC可实现正弦信号的产生。-Based on CORDIC achieve sinusoidal signal simulation by using built-in IP core CORDIC can achieve sinusoidal signal.
counterbasedDPWM_D
- 基于计数器的数字脉宽信号调制，用于电力电子设备pwm信号的产生-counter based digital puls width modulator
process
- 利用VHDL硬件描述语言来实现正余弦信号的产生-Using the VHDL hardware descr iption language to achieve the generation of a positive cosine signal
基于FPGA开发的DTMF信号的产生
- 用verilog写的，是基于FPGA的开发，已经成功的仿真过。(Written in Verilog, has been simulated.)