搜索资源列表
CUS_SPI-VHDL
- 此为VHDL的SPI通信代码，全部在一个压缩包中，请仔细阅读后再使用．-this as VHDL code SPI communication, all in a compressed package, please read carefully before use.
mc8051V1.4
- 8051硬核源码（VHDL），具有全部VHDL代码、测试环境以及说明文档、综合脚本等完整的开发、验证环境，源代码通过ASIC投片，并得到不断完善-8,051 hard-core source code (VHDL), with all VHDL code, testing and documentation, environment, Comprehensive integrity of the scr ipt, such as development, certification, the s
DS18B20+VHDL
- 用VHDL语言实现的控制DS18B20构成测温仪表的程序，包含了全部代码，可显示最高精度-with VHDL control DS18B20 constitute Thermometer procedures, contains all the code will show that the most high-precision
pci
- pci接口的verilog原代码,定义了pci接口所需要的全部引脚
SongQuartusVHDL
- 乐曲硬件演奏电路设计的全部VHDL代码，在QuartusII环境下编译通过，已存在QuartusII项目
8051的内核(vhdl)
- 最完整最实用的8051的软核，用VHDL语言编写全部原代码，并有详细的注释介绍，对开发增强型多功能单片机或RSIC单片机内核和单片机SOC应用非常有参考价值-most complete most practical of the 8051 soft-core, with all the preparation VHDL source code, and the Notes for a detailed briefing on the development of an enhanced mult
CPU_16.rar
- vhdl语言的16b cpu代码 全部的代码我会依次上传 另有说明txt文本,VHDL language 16b cpu code all the code I will upload the text otherwise stated txt
I2C_Interface(VHDL)
- I2C总线接口FPGA的实现代码，全部为VHDL语言源码文件，内附设计实用说明文档。-I2C bus interface FPGA implementation of the code, all source files for the VHDL language, included the design and practical documentation.
rel_08_done
- 修改自OpenCores的黑白棋游戏代码。采用VGA输出显示，PS2键盘（W、A、S、D、回车）输入控制，实现AI，LED灯指示是否游戏结束，VGA显示频率25MHz，系统频率50MHz，经过Cyclone IV芯片EP4CE115F29C7N的板级调试，实现全部功能，文件夹下有rtl源代码，管脚定义pin文件，和可以直接进行JTAG烧写和E2PROM烧写的pof和sof文件，-Modified from OpenCores Othello game code. Using the VGA ou
QuartusIIandModelSim
- 本文主要描述了如何在QUARTUS II 中输入程序文件，生成网表及标准延时文件，然后通过 MODELSIM进行功能仿真与后仿真的过程，主要为图解，含全部代码及仿真波形。 -This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation
61EDA_C2293
- 《设计与验证Verilog程序》书中的全部代码，很全-" Verilog Design and Verification procedures" all the code book, it is full
ep1c6_32_vga
- vga控制在EPC16上面的实现代码，包括qartus下的全部源码-vga control EPC16 the realization of the above code, including all the source code under the qartus
MP3
- MP3解码的ASIC全部过程，包换含c和vhdl代码，样例。-MP3 decoding ASIC whole process, shifting with c and vhdl code, sample.
fadder32
- 短代码实现32位全加器，带经Quartus II9.1编程测试全部文件-Short code to achieve 32-bit full adder, with programming tested by the Quartus II9.1 all documents
system-generator--BPSK
- 基于system generator 的BPSK 全数字通信机（原创论文+全部代码d-Based on the generator system. BPSK digital communication equipment (original papers+ code
clock
- 实验3设计资料简易时钟 FPGA数字时钟设计参考资料及全部代码-Experimental design simple clock FPGA digital clock design reference information and all the code
55593402DDS_vhdl
- DDS分频实现，全部代码的完整过程，包括截图等-DDS divider to achieve the complete process of all the code
uart_tx_rx
- 在altera的FPGA平台上实现rs232串口的自收发通信，速率为115200波特率，PC机使用串口调试助手即可观察结果。包含全部代码与工程，本人亲自测试通过。-Realization of self transmitting and receiving communication serial port of RS232 In altera on the FPGA platform, at a rate of 115200 baud rate, PC using serial debuggi
VGA_caidai_zifu_juxing
- verilog实现VGA显示的代码，包括驱动，时钟管理，显示的全部，代码中包括三个实例，一个最常见的八个彩带型，一个矩形框，一个魔幻彩带显示实现，全部代码实现。-verilog implementation code VGA display, including the driver, clock management, all of the code displayed include three instances, one of the most common type of eight
gmsk
- 利用fpga实现gmsk的调制并仿真，全部代码(Fpga implements gmsk)