搜索资源列表
keyboard__1.1
- 实现数码管输入显示器输出功能（加减乘除运算）-realization of the digital input output function display (arithmetic operations)
calculation2
- 用VHDL语言实现0--100范围内简单计算器功能的源代码，包括加减乘除四种运算功能-VHDL 0 -- 100 within a simple calculator function in the source code. including the four arithmetic operations function
cpu
- 实现了CPU的基本功能，含加减乘除等运算的实现，VHDL版
ALU.zip
- VHDL实现cpu核心逻辑与运算单元模块的实现，完成4bit*4bit输入8bit输出的运算，可做加减乘除逻辑移位6种操作,the implementation of Arithmetic and logic unit based on VHDL, can do as the adder,subtractor,multiplier,divider,shifter and logic operation.
fudianshuyunsuan
- 介绍一组浮点数的运算代码，包括加减乘除运算的VHDL代码实现-Introduced a set of floating-point code of the operation, including addition and subtraction multiplication and division operations to achieve the VHDL code
Double_FPU
- 详细介绍双精度浮点数据的格式，以及加减乘除运算的实现方法-Details of the format of double-precision floating-point data, and the realization method of addition and subtraction multiplication and division
alu
- 用VHDL实现8种运算的ALU，带鱼不带符号的加减乘除，与或异或和求反-Use VHDL to achieve the eight kinds of computing ALU, hairtail unsigned addition and subtraction, multiplication and division, with or XOR and seek anti-
CPU
- 利用vhdl模拟实现CPU的功能，实现其中的加减乘除等多种运算-CPU utilization of vhdl simulation of the realization of the function, the realization of which, such as addition and subtraction, multiplication and division multiple computing
add8
- 用VHDL语言实现的八位计数器 可进行简单的加减乘除运算-It is a counting device with eight-bit that could plus ,subtract ,multiply and divide.
alu8
- 计算机中央处理器硬件中的核心部件，算术逻辑运算单元的实现，包括加减乘除，左移，右移，大于等等。-Computer hardware in the CPU core components, arithmetic logical unit implementation, including addition and subtraction multiplication and division, left, move right, than so.
final3
- FPGA实现计算器（四位以内加减乘除，逻辑运算，包含优先级）-FPGA realization of calculator (four less than addition, subtraction, logical operations, including priority)
signed_add
- verilog 中处理有符号数加减乘除运算的详细讨论和例子。 -Verilog signed arithmetic discussion and examples
verilog_calculator
- 一个Verilog写的简易计算器。能进行二进制加减乘除运算，操作数通过按键输入并用数码管显示。当按下运算符号键后，计算器进行两个数的运算，数码管将结果显示出来。-A simple calculator written in Verilog. Binary addition and subtraction to multiplication and division, operating a few keystrokes and use digital display. When the pres
CPU
- 简单CPU的实现，包括加减乘除运算和逻辑运算、移位运算等，可运行。-Simple CPU implementation, including addition, subtraction and logical operations, shift operation can be run.
verilogcalculator
- 简易的计算器，可实现加减乘除运算，采用verilog编写-Simple calculator, addition, subtraction operation can be realized using verilog prepared
calculator
- 简易的计算器，可实现加减乘除运算，采用verilog编写-Simple calculator realized by verilog,which could operate addition and subtraction process
jisuanqi
- 简单的计数器，可以乘除加减运算，可以连续的坐加减乘除运算-Simple counter, multiplication and division addition and subtraction operations, addition, subtraction operation can be continuously sitting
digtal-experiment
- 8位计算器的设计,可以实现有效数字为8位的有理数的加减乘除运算,同时运用状态机,可以实现连续计算功能-8 calculator is designed to achieve an effective figure of eight of the rational number arithmetic operations, while the use of state machines, can achieve continuous computing
jisuanqi
- fpga开发板实现按键两位数加减乘除运算。通过数码管显示-FPGA development board to achieve key two digit add, subtract, multiply and divide operations. Through the digital tube display
jsq
- 基于FPGA的计算器，可以实现加减乘除运算功能，由于时间问题，浮点运算未能实现，其中的二进制与BCD码相互转换的模块可以使用-FPGA-based calculator, arithmetic calculation function can be achieved, due to time issues, floating-point operations failed to achieve, including binary and BCD code conversion modules t