搜索资源列表
Convolutional encoding and Viterbi decoding with k
- 卷积码编码和维特比解码 当K为7 时 供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
conv_code
- 用VHDL实现卷积码编码，该码为（2.1.3）型卷积码。-using VHDL Convolutional coding, the code (2.1.3) - Convolutional Codes.
gongcehngsheji_477-2
- 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
viterbi
- 卷积码编码及其Viterbi译码的实现
convolution_encoder_VHDL
- 卷积码编译码,由SERVICE、PSDU、TAIL和PAD域组成的DATA域应进行卷积编码，码率应根据所需的传输速率从R=1/2,2/3,3/4中选择-for 802.11a simulation WLAN FEC convolution_encoder g0=133 g1=171 Rate 0:1/2 1:2/3 2:3/4 for 802.11a simulation
viterbi
- verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
cc_encode
- 卷积码，并行编码，FPGA，通过了测试验证-CC Code， Parallel Coding， FPGA
123
- 将通过仿真的VHDL 程序下载到FPGA 芯片EPF10K10LC84-3 上，取得了较为满意的结果。本设计选择的(3,1,2)卷积码和（2,1,1）卷积码,都是极具代表性的卷积码。因为卷积码具有相似的结构和特点，所以(3,1,2)卷积编码器和（2,1,1）卷积解码器的设计思想，具有普遍适用性。-Through the simulation of the VHDL program downloaded to the FPGA chip EPF10K10LC84-3, the obtained s
conv_enc
- 卷积码编码，用veriolog实现一个（2,1,3）卷积编码-Convolutional coding, with veriolog implement a (2,1,3) convolutional code
abc
- 卷积码编码器的实现，用的是vhdl语言。这是毕设时做的，已经调通。-Convolutional code encoder implementation, using vhdl language. This is done when the complete set has been transferred through.
FPGA-convolutions-encoder
- 卷积码是数字通信中很重要的一种差错控制编码 具有很好的性能,用硬件的形式描述具有速度快，便于修改的优点，通过该种方法设，计的编码器经测试运行可靠正确。-Convolutional codes are very important in digital communication error control coding with a good performance, with the descr iption of the hardware in the form of a fast, eas
cConnvolutiono
- 卷积码编码与维特比解码 当K为7 时 供大家参考-convolutional encoding and Viterbi decoding with k 1 2 7 rate
encoding-decoding
- 卷积码编码译码程序以及其modelsim仿真波形文件等-Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file
viterbi_hard
- (2,1,3)卷积码编码，硬判决译码；编码是matlab语言，译码是verilog语言-(2,1,3) convolutional code encoding, hard decision decoding coding is matlab language, decoding is verilog language
viterbi_soft
- (2,1,3)卷积码编码，软判决译码；matlab语言编码；verilog语言译码；-(2,1,3) convolutional code encoding, soft-decision decoding matlab coding verilog decoder
conv_encode
- 本设计是一个基于FPGA的咬尾卷积码编码器设计，要求使用verilog语言编写编码器模块，通过编译和综合，并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by c
conv_encoder
- TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码-Tail-biting convolutional code encoder verilog code
www
- 卷积码编码器卷积码是1955年由Elias等人提出的，是一种非常有前途的编码方法 一些资料上可以找到关于分组码的一些介绍-Convolutional code encoder
cycle_en_decoder
- 卷积码编码/解码，Verilog语言实现，带仿真程序。-Convolution encoder/decoder, Verilog language, with a simulation program.
（2,1,3）卷积编码和viterbi译码
- 自己写的（2,1,3）卷积编码器和viterbi译码，测试已通过