搜索资源列表
juanji2
- 用TI DSP汇编指令进行程序设计：“TIC54XDSP汇编程序设计-卷积-compiled using TI DSP Programming instructions : "TIC54XDSP compilation of program design-convolution
DCT_1D
- 一维DCT变换的verilog源码，可用于JPEG算法优化的参考。程序中用到的算法称为“扭卷积”，可参考相关IEEE paper
coverlater
- 本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码，能够成功地编译和仿真。
BCDconv
- BCD编码的Verilog HDL程序，能够实现BCD编码与卷积码。
juanjima
- 卷积码的生成程序,为(2,1,3)移位寄存器的卷积码生成-Convolutional code generation process for the (2,1,3) convolutional code of the shift register to generate
chengxu
- 一个分频器，一个卷积编码器的程序，都是VDHL的-A frequency divider, a convolutional encoder program, are VDHL of
viterbi
- verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
conv_enc
- 这是一个用VERILOG HDL编写的卷积码程序-This is a VERILOG HDL with the preparation of procedures for the convolutional codes
Convolutionalencoder
- 应用VHDL语言实现的卷积编码器的应用程序-Application of VHDL language implementation of the convolutional encoder applications
123
- 将通过仿真的VHDL 程序下载到FPGA 芯片EPF10K10LC84-3 上，取得了较为满意的结果。本设计选择的(3,1,2)卷积码和（2,1,1）卷积码,都是极具代表性的卷积码。因为卷积码具有相似的结构和特点，所以(3,1,2)卷积编码器和（2,1,1）卷积解码器的设计思想，具有普遍适用性。-Through the simulation of the VHDL program downloaded to the FPGA chip EPF10K10LC84-3, the obtained s
juanji
- FPGA的卷积编码小程序，VHDL描述，参数为2，1，7.-2,1,7 cov with VHDL.
conv_enc
- 该程序文档是用verilog实现卷积码的编码和解码，报告中从原理进行详细的分析，代码程序也有详细的备注-The program document is to achieve convolutional code with verilog coding and decoding, the report analysises the principle ,the code also has a detailed program note.
Viterbi_verilog
- 在ISE环境下用Verilog语言编写的卷积码程序及Viterbi译码程序-Under the ISE Verilog language with procedures and Viterbi convolutional code decoding program
convolution
- convolution卷积码生成器程序设计及仿真源代码-convolution convolutional code generator source code of program design and simulation
encoding-decoding
- 卷积码编码译码程序以及其modelsim仿真波形文件等-Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file
FileRecv
- 卷积编码的有关介绍，有关论文，以及有关matlab程序代码-Convolutional code introduced the paper, as well as the Matlab code
convotion_decode
- 用verilog写的卷积码的编码程序以及viterbi译码程序-Use verilog write convolution code coding procedures and viterbi decoding program
juanji1
- 本程序是在Xilinx ISE上编写的，它完成（2,1,6）卷积码的编码工作。里面有源程序和用以仿真的测试文件-The program is written on Xilinx ISE, it completed the (2,1,6) convolutional code encoding. Source and for the simulation of the test file inside
Convolution
- 卷积程序的Verilog程序，实现卷积功能(Convolution program Verilog program to achieve convolution function)
卷积码程序verilog
- 用Verilog语言在FPGA下实现卷积程序。(Convolution code utilite by verilog)