搜索资源列表
keyboard
- 矩阵键盘的vhdl编程,非常的实用,带有去抖动
key
- 基于可编程逻辑器件FPGA的独立式键盘设计，内部具有硬件去抖动电路。值得一看
Verilog_Design
- Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.
debounce
- 基于VHDL的键盘去抖动电路 基于VHDL的键盘去抖动电路-VHDL-based keyboard to jitter circuit VHDL-based keyboard to jitter circuit
an_jian_qu_dou_dong
- 可以用于按键去抖动的电路应用，采用vhdl编写-Button can be used to jitter circuit applications, the preparation of the use of VHDL
qudou
- 通用的基于状态机的VHDL按键及信号去抖动模块，非常有用-Generic VHDL-based state machine keys and signal to the jitter module, very useful
an_jian_qu_dou_dong
- 基于FPGA实现的按键去抖动电路设计，解决了按键抖动的问题-abcdefjgajgasg
key_xiaodou
- 本例中用状态机实现了消抖电路： 端口描述：clk 输入检测时钟；reset 复位信号；din 原始按键信号输入； dout 去抖动输出信号。-In this case the state machine used to achieve the elimination shake circuit: Ports Descr iption: clk input test clock reset reset signal din original key signal input dout t
Debounce
- VHDL编写。在CPLK开发板上设计的数字钟的去抖动电路。该模块相对独立，是学习去抖动的好资料。该模块跟我其它的8个模块配套构成一个数字钟。-Programmed with VHDL.A debouncing circuit which is part of a digital clock designed on a CPLD development board.The module is independent from others and is useful for learning de
qudou
- 实现了按键的去抖动功能，板子上调试，比较好用-To achieve a de-jitter function keys, board debug, relatively easy to
qudou
- 此源代码为去抖动模块代码，代码简洁易懂，并已仿真成功，可以下载。-The source code for the debounce module code, the code easy to read, and has been successful simulation, you can download.
qudoudong
- 多按键去抖动电路VHDL源码，按键个数参数化，每个按键处理调用了上面的模块：-Many buttons to dither circuit VHDL source, the number of key parameter, each key, the call to the treatment of the above modules:
ep1c12_6_key_debounce
- 按键去抖动设计，已经在试验箱上验证通过。-Button debounce design has been verified on the test chamber
keyboard
- 实现从键盘输入的vhdl程序，通过按键输入，扫描，键盘去抖动，键盘输出-input from the keyboard
keyqudou
- fpga verilog hdl 设计键盘去抖动程序，设计环境quartusii 9.0。仿真绝对通过。-fpga verilog hdl design keyboard to jitter program design environment quartusii 9.0. Simulation absolutely pass.
edge_catch
- 信号去抖动处理程序，通常在时钟沿到来时，信号出现不稳定，这个程序可以处理-signal process jitter
Button
- xilinx FPGA 按钮延时去抖动实验-xilinx FPGA button to delay jitter test
Lab15_sw2reg
- 开关数据加载到寄存器并显示的设计与实现.3． 设计一个可以把4个开关的内容存储到一个4位寄存器的电路，并在最右边的7段显示管上显示这个寄存器中的十六进制数字。我们使用到去抖动模块clock_pulse， 用btn[0]作为输入；8位寄存器模块，用btn[1]作为加载信号；7段显示管上的显示模块x7segbc；分频模块clkdiv，用以产生模块clock_pulse和x7segbc的clk190时钟信号。-Design of switching data is loaded into the re
key_alone
- 4x4矩阵键盘扫描 去抖动 带编码输出 模块打包-the program of key scan
Quartus按键去抖动程序
- Verilog语言编写的按键去抖动模块demo(Key debounce module demo written in Verilog language)