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huaqiaodaxue--DE2_NET
- 华侨大学专用实验程序代码，实现de2网络发送数据包，华侨大学实验室。 华侨大学eda实验室专用-Chinese University of dedicated experimental program code, data packets sent over the network to achieve de2, Huaqiao University laboratory. Huaqiao University eda laboratory dedicated
3ADataSending
- Sparten-3A板发送程序，用于发送数据包。-Sparten-3A board data sending
3ASendReceive_SpaceDiffData_console
- Sparten-3A收发_间隔产生不同分组_控制程序，用于发送数据包。-Sparten-3A transceivers have different groups _ _ interval control program, used to send packets.
3ASendRecieve_SpaceSameData_Console
- Sparten-3A收发_间隔产生相同分组1_控制程序，用于发送数据包。-Sparten-3A have the same group receive _ 1_ interval control program, used to send packets.
3ASendReceive_SameData101110_Console
- Sparten-3A收发_间隔产生相同分组101-110_控制程序，用于发送数据包。-Sparten-3A interval produced the same group receive _ 101-110_ control program, used to send packets.
3ASF_SameData10110-11001_Console
- Sparten-3A收发_间隔产生相同分组10110-11001_控制程序，用于发送数据包。-Sparten-3A transceiver _ interval produce the same grouping 10110- 11001_ control program, used to send packets.
VHDL_LAPS
- 简化LAPS协议，对发送的数据包进行封装、传输和接收，，包含FCS是对整个LAPS帧进行CRC校验。-Simplify LAPS protocol, encapsulation, transmission, and receiving the transmitted data packet, containing FCS is performed on the entire LAPS frame CRC.
t1_comm
- 该程序包括数据的发送，加密，奇偶校验，接收，解密等模块，实现了一个完整的收发操作。为了测试方便，我们将接收到的数据直接引入发送端口，为此，我们编写了测试脚本文件，验证程序的正确性。该程序模块较多，读者可参考压缩包内的原理框图文件，以便于理解。-The program includes sending, encryption, parity, receive, decrypt data modules to achieve a complete transceiver operation. In
WITH_LED_RUN
- 上位机通过PCI9054和fpga通讯，例子中为主机发送包，传到pci9054,然后pci9054把数据发给fpga，fpga收到数据控制LED-PC communication through the PCI9054 and fpga examples for the host to send packets transmitted pci9054, then send the data pci9054 fpga, fpga receive data control LED
FPGA_Project_Files
- 此例为FPGA发送数据包到pci9054，用到fifo模块，还有sram模块，比较复杂。应用在pci9054与fpga通讯-This example sends the packet to the FPGA pci9054, use fifo module, as well as sram module, is more complex. Application pci9054 communication with fpga
UART
- 在DE2开发板上实现串口收发设计，系统时钟频率为50MHz,reset信号低电平有效，输入数据最高位为1时按位取反再输出-Achieve serial transceiver design DE2 board, the system clock frequency of 50MHz, reset active low signal, the input data is the most significant bit is 1. Bitwise re-export Google 翻译（企业版
ethernet_loopback
- 通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the ne