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用一位全加器组成四位全加器
- 用一位全加器组成四位全加器. 所用语言是Verilog HDL. 主要用在加法器的设计中。-All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design.
adder4_1
- 这是用vhdl编写的四位加法器，请多指教-this is the preparation of the four VHDL Adder, please enlighten
adder_4bit
- 四位加法器，用OrCAD完成，可用于八位乃至十六位加法器的设计原型-four adder with OrCAD completed, can be used for eight or even 16 Adder design prototype
eecadd_8
- 此程序用VHDL语言编写，在四位加法器基础上完成8位二进制加法，输出是BCD码
add4
- 一个四位加法器的VHDL语言实现，并通过编译测试-A four-adder realization of the VHDL language, and compile test
4bit_buma_adder
- Verilog作业 ：自己写的源码输入，补码输出的，由状态机控制的四位加法器，为保证时序，加法器模块为超前近位加法器，包含测试台，通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing
chapter7
- VHDL 四位加法器 利用quartus II开发四位加法器，-VHDL comptur comparator_4
mux4
- 基于VHDL的四位加法器的实现，通过此加法器的设计，可以扩展到更多位的加法器的设计-VHDL-based implementation of the four adder, through the design of this adder, can be extended to more bits Adder
adder4
- 这是一个用verilog编写的四位加法器，编程环境是xilinx ise10.1.-This is a written with the four adder verilog, programming environment is xilinx ise10.1.
add4
- 四位加法器verilog源代码，经过modelsim仿真验证正确，用ISE7.1i以上版本打开工程文件。-Four adder verilog source code, right after the modelsim simulation with ISE7.1i later open the project file.
multiply
- 四位加法器的VHDL代码，实现四位加法器FPGA实现。-Four adder VHDL code to achieve the four adder FPGA.
count4
- 四位加法器的Verilog实现，可以实现综合工具对其综合-Four adder Verilog implementation of their comprehensive synthesis tool can
adder4_1
- 基于VHDL的四位加法器，运行环境quartus-VHDL-based four adder, operating environment quartusII
four-adder-design
- 可编程逻辑设计-用VHDL语言进行四位加法器的设计-Programmable logic design _ four adder design
UDP
- 这是用Verilog HDL编写的程序 利用UDP方法实现四位加法器-This is written in Verilog HDL programs Use UDP method four adder
adder4bit
- VHDL设计的四位加法器器，仿真测试正确，可以使用。-VHDL design of four adders, a simulation test correctly, you can use
adder_4
- 四位加法器的三种实现方法，包括行为级描述、行波进位加法器、超前进位加法器-Three of four adder implementations, including behavioral descr iptions, ripple carry adder, look-ahead adder
EDA
- EDA小程序，用VHDL语言设计七人表决器，四位加法器。-EDA small program design using VHDL seven people voting, four adder.
adder
- 实现四位加法器，适合初学者学习VHDL语言(it's an addler of four bits which is designed for the new designer of VHDL)
y210
- 三八译码器，四位加法器，EDA实验，用verilog编写(EDA experiment with verilog language)