搜索资源列表
mt48lc2m32b2
- SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified
SDRAM_C
- SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified
FullAdder
- 四位全家器的VHDL语言模块，已经在ISE8.1上经过测试通过-family of four VHDL modules, has been tested on ISE8.1 through
bmul32_test
- 32位并行乘法器的测试文件，已经经过验证，可以直接使用
dual_port_ram
- 实现双口ram的读写功能，并含有测试文件，已经经过方针验证，很好用的-the writing and reading to the dual port ram ,good
i2c_AT2402
- 用VHDL语言编写的AT24C02程序，并用数码管显示，本程序已经经过本人测试过，很好用-The AT24C02 is available VHDL language program, and use digital tube display, this procedure has been tested himself, very good to use--
mcode_FPGA
- 伪随机码发生器，次源码已经经过了测试并通过时序仿真验证没有任何问题，此小m序列发生器的特征多项式我没有写，但我建议大家在看原代码之前还是先看下扩频通信中m、M、Gold序列的原理，只有这样才能够真正的明白伪随机码发生器发生器的原理。-mcode_FPGA
MyUART
- 经过我严格测试，已经获得实际应用的RS232串口通讯的VHDL编写的程序，对于初学者绝对有帮助！-After I tested, has received the application of the RS232 serial communication program written in VHDL, for absolute beginners help!
DSP_INTERFACE
- DSP与FPGA时序接口模块，已经经过测试，保证读写稳定-The Interface of DSP to FPGA
ads1675_if
- verilog时序图编写和测试代码，代码完整已经经过测试可以运行。-verilog timing diagram writing and testing code, the code has been tested to the full run.
I2C_EEPROM
- 1. 本测试是夏宇闻 verilog数字系统设计教程，中的例程。 2. 编译环境Quartusii 3. 仿真环境Modelsim se 6.5d 4. 可综合部分已经经过quartus 验证正确 5. 仿真部分通过将I2C模块与一个EEPROM模型组合，通过时序仿真-EEPROM_I2C Verilog
SPI_Master_module
- 利用VHDL语言编写的SPI主机模块，采用内部自环回已经经过测试，发送接收数据正常，里面有modelsim工程，可以验证下仿真波形-SPI host module using VHDL language, has passed internal self-loopback test, sending and receiving data normally modelsim project, which can be verified under simulation waveforms
tft_lcdPili9325
- tft驱动，放心使用吧，经过测试已经是完好的了，如假包换-TFT driver, feel free to use it, after the test is in good condition, such as the original
VERILOG-CAR-TEST
- 基于FPGA的Verilog语言的智能小车，已经经过测试。-FPGA-based smart car Verilog language, and has been tested.
my_uart2
- 基于FPGA的串口通信源代码。已经经过调试助手测试，-Release 13.2- WebTalk (O.61xd) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Project Information -------------------- ProjectID=BFC2DD71D6FA404A87FDA640DB4B5999 ProjectIteration=14 WebTalk Sum
sp605_pcie_13.2
- 基于FPGA，pcie开发的源码程序，已经经过测试，上传来给其他爱好者学习交流。- input user_clk, input user_reset, input user_lnk_up, // Tx input [5:0] tx_buf_av, input tx_cfg_req, output tx_cfg_gnt,
i2c
- 一个非常好用的verilog I2C程序。已经经过测试可用-A very good use of I2C Verilog program. Has been tested and can be used