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watchver
- 一个VHDL编写的时钟的程序，全部源代码打包上传-The clock to prepare a VHDL process, all source code packaged Upload
machester_VHDL
- manchester码在通信领域中用途广泛 这个VHDL程序包括曼彻斯特码的打包和解包。。很难得哦-manchester code in the communications area of a wide range of uses of this process includes the VHDL code packaged Manchester reconciliation package. . Oh, a rare
seg7_controller
- 七段译码器循环显示，并打包为IP核，可在其他程序中使用，已调试，可用。-Seven segment display decoder loop, and packaged as IP cores, can be used in other programs have debugging available.
led_seq_demo
- 跑马灯的打包verilog程序，包括v和ucf,以及能直接下载的xise文件-The Marquee verilog program package, including v and ucf, and can be downloaded directly xise file
clock
- 闹钟 运用quartus2软件编写程序，具有调整时间，设置闹钟，整点报时等功能，将整个工程打包了-Alarm Clock using quartus2 software programming, adjust the time, set the alarm, the whole point timekeeping function, the whole project package
VHDL
- 数字电路实验程序代码打包下载 版本 宁波大学学年数字电路实验 VHDl编程 部分 -Digital circuit experiment program code package download version Ningbo University academic year programming section VHDl digital circuit experiment
CLK_DIV_IP_packager
- Vivado IP packager的实例。Vivado版本2014.2，使用Verilog语言对一个分频程序打包。-Examples of Vivado IP packager. Vivado version 2014.2, using the Verilog language for a division of the program package.