搜索资源列表
cic_4_dec
- 实现4倍抽取的CIC抽取滤波器模块的Verilog实现，在对数据进行抽取之前，首先进行滤波
shuzixiabianpin
- 数字下变频中cic滤波器，级联三级，主要功能是抽取滤波，及重要参考资料，包括数字下变频论文-Digital down conversion of cic filter, cascade three-level main function is to extract the filter, and important reference materials, including digital down conversion papers
cic
- 抽取滤波的Verilog实现，经测试可用-Decimation filter
ddc_program
- 本程序处理的是一路16位的DDC，用DSP48实现脉动式的滤波，四倍抽取-This procedure is the way 16-bit DDC, pulsating with DSP48 filter implementation, taking four times the
HalfbandDec
- 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
cic
- 积分梳状滤波器的硬件实现，主要是实现在允许范围内进行抽取滤波，实现数据压缩-failed to translate
cic_cq
- 在altera平台用verilog硬件描述语言实现cic抽取滤波，包含完整的工程代码，已经仿真通过，可以直接用于实践-In the Altera platform using Verilog hardware descr iption language CIC decimation filter, contains the complete project code, has been adopted by simulation, can be used directly in practice
DDC中的抽取滤波器设计及FPGA实现
- 本文对下变频模块中抽取滤波进行了详细的分析，并详细阐述了其FPGA的实现过程和方法(In this paper, the decimation filtering in the down conversion module is analyzed in detail, and the realization process and method of FPGA are discussed in detail)
CIC
- 包括地址产生单元、数据查询单元（可以重新初始化rom中的数据，由matlab产生.coe文件替换）、积分单元、抽取单元、梳状滤波单元，对于初学者很有帮助(Including address generation unit, data query unit (data can be re-initialized in rom, generated by matlab. COE file replacement), integration unit, extraction unit, comb fi