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LED七段译码
- 初次上传文件，采用文本格式编辑内容，不知道是否妥当，如有不便之处，敬清各位原谅。-initial upload documents using text format editorial content, I do not know whether they are appropriate, if any inconvenience, King - forgive me.
int2bit
- 整型数据转换为二进制数据的实验。全部都是整个文件夹上传的。可以用QUARTUS2直接运行的。
pwm
- 在SPARTAN 3E开发平台上，利用其板子上一些I/O口或LED来实现PWM的设计 上传文件中pwm_ctrl是用picoblaze实现的PWM控制文件，另外一个则是在ISE设计中的顶层文件。
Common_multiplier_verilog_design
- 上传文件为：常用乘法器verilog设计.rar-Upload files as follows: common multiplier verilog design. Rar
Common_adder_verilog_design
- 上传文件为：常用加法器verilog设计.rar-Upload files as follows: common adder verilog design. Rar
Fpgamemtest
- 这个是用vhdl语言描写的关于测试FPGA内存的代码。用reset复位，包括.vhdl .ucf .bit文件。我只上传了这3个最重要的。-test memory,including .vhdl .ucf and .bit file~
Lab2
- xilinx培训资料，配合相应的PDF文件使用 共20个，先上传一部分，其他的有需要再上传-xilinx training materials, with the corresponding PDF file using a total of 20, first upload a part of, the other the need to re-upload
Lab4
- xilinx培训资料，配合相应的PDF文件使用 共20个，先上传一部分，其他的有需要再上传-xilinx training materials, with the corresponding PDF file using a total of 20, first upload a part of, the other the need to re-upload
ISE_lab2(2)
- xilinx培训资料，配合相应的PDF文件使用 共20个，先上传一部分，其他的有需要再上传-xilinx training materials, with the corresponding PDF file using a total of 20, first upload a part of, the other the need to re-upload
ISE_lab4
- xilinx培训资料，配合相应的PDF文件使用 共20个，先上传一部分，其他的有需要再上传-xilinx training materials, with the corresponding PDF file using a total of 20, first upload a part of, the other the need to re-upload
Lab1
- xilinx培训资料，配合相应的PDF文件使用 共20个，先上传一部分，其他的有需要再上传-xilinx training materials, with the corresponding PDF file using a total of 20, first upload a part of, the other the need to re-upload
Lab3
- xilinx培训资料，配合相应的PDF文件使用 共20个，先上传一部分，其他的有需要再上传-xilinx training materials, with the corresponding PDF file using a total of 20, first upload a part of, the other the need to re-upload
led_3_test
- 本源码实现了基于FPGA的3寸OLED的驱动，并能在屏上实现条纹显示和棋盘格显示。所使用开发板是CYCLONE 3,上传源码是整个工程，里面有源程序文件-The source implementation of FPGA-based 3-inch OLED driver, and can be implemented on-screen display and stripes checkerboard display. Development board used is CYCLONE 3, u
EDA-experiments-based-on-VHDL
- 上传的文件包括E有关EDA实验的程序，比如FIFO，秒表，数字钟，七段数码管，状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
even_divider
- 第一次上传文件，已通过仿真测试，可以实现任意的偶数倍分频-Achieve any even frequency divid
Desktop
- 用单片机做的LED灯，里面在有几个文件了，如果上传不了，别怪我-Using single-chip LED lights, which in a few files, if you can not upload, do not blame me
multiplier
- 8*8的乘法器基于quartus2的显示文件，其中使用了门电路和全加器来实现的，全加器用以实现进位运算，由于是第一次上传文件，这个是基于quartus2的显示文件-8* 8 multiplier, which uses the gate and full adder to implement the full adder to achieve binary operations
risc_cpu
- RISC_cpu，包括所有的模块与测试文件。是夏宇闻第二版书中的错误均已改正，运行正确后上传，请放心使用。-RISC_cpu, including all modules and test files. Xia Wen error of the second edition of the book have been correct, to run correctly upload, please feel free to use.
ALL_6
- 这是项目总的文件夹，包括原理图，PCB,上位机VC程序，驱动程序，下位机FPGA程序，可做为开发板，LVDS采集开发板，前面上传的5个位五个测试程序，已经验证其正确性，需要的可以参考。-This is the total project folder files, including schematics, PCB, PC VC, the driver, the next crew FPGA program can be used as the development board, LVDS c
DS28E01_final
- 基于SHA-1算法和DS28E01加密芯片的FPGA系统设计，该上传文件为整个设计的系统文件。Quarter软件编程的Verilog程序，包含仿真调试界面。-Design of FPGA system based on SHA-1 algorithm and DS28E01 encryption chip。