搜索资源列表
the-design-of-16-bit-cpu
- 用vhdl硬件语言设计的16位cpu，上传的压缩包既包含源代码又包含详细的文档说明。-with vhdl hardware design language of the 16 cpu, Upload compressed contains both the source code also contains a detailed document shows.
DDS_Core_HSpeed_ADDA_C5H
- ＦＰＧＡ的按键调试，不知道怎样上传整个的文档，就上传个程序，大家可以借鉴下-FPGA debug keys, do not know how to upload the whole document, you upload a program, we can learn from the next
T01_UART_CORE
- Verilog 实现的 UART串口读写控制核 参数化校验、时钟设置，完整工程（xilinx），包括文档、源码等。供学习参考，希望大家上传自己代码，共同提高，打倒小日本。-Verilog implementation of the UART serial port to read and write control nuclear parametric check, clock setting, complete project (Xilinx), including documentation
lab2
- 上传的文档以及代码是利用system generator来实现一些简单功能的实例，主要给system generator初学者一些参考-Here are some examples of entry-system generator, mainly for beginners some reference
lab4
- 上传的文档以及代码是利用system generator来实现一些简单功能的实例，主要给system generator初学者一些参考-Upload documents and code using system generator to implement some simple examples of functions, primarily to beginners some reference system generator
lab5
- 上传的文档以及代码是利用system generator来实现一些简单功能的实例，主要给system generator初学者一些参考-Upload documents and code using system generator to implement some simple examples of functions, primarily to beginners some reference system generator