搜索资源列表
vga_top
- VGA测试程序顶层文件，为视频信号的处理提供框架-Top-level test program files VGA, for video signal processing to provide a framework
EDA
- VHDL上机手册（基于Xilinx ISE） ___________________________________________________ 1 ISE 软件的运行 2 创建一个新工程 3 创建一个VHDL源文件框架 4 输入VHDL程序 *5 仿真 6 创建Testbench波形源文件 7 设置输入仿真波形 -eda
BUIW_framework
- 这是一篇关于buiw的框架说明文档，很值得学习。-It display buiw framework！
fir_1
- 这个FIR滤波器是基于ALU框架编写的，仅供参考使用-The FIR filter is based on the framework of the preparation of ALU, the only reference to the use of
FSM
- 一种简单的状态机，本程序为初学者提供了一种编制状态机的框架。-a kind of simple FSM。
vga_interface
- 以VHDL撰写的萤幕VGA控制程式，有渐层显示功能与框架建立功能。-To write VHDL VGA screen control program, there is a gradient set up in the frame display.
Frame_2D
- 自己编写的通用2维框架结构，可以计算模态、静力、动力响应-A 2D frame building of ANSYS developed by myself, can calculate modal, static and dynamic response
predistortion
- WCDMA数字直放站中数字预失真研究的框架和其FPGA实现-Digital Repeater WCDMA digital pre-distortion of the framework and its FPGA implementation
isolator
- 隔震模型，框架，东南沿海，十二层，V6-Isolation model, framework, south-east coast, second floor, V600
3rd-First-App
- MSTAR平台上的第一个3RD应用程序，对于MSTAR平台刚入门，并且不知道如何编写第三方应用程序的开发者很有帮助。这是一个3RD程序的基本的框架-MSTAR platform, the first 3RD application platform for the MSTAR has just started, and do not know how to write third-party applications developers helpful. This is a basic pro
fsm
- 由于工作原因，需要开发一套有限状态机框架，在此和大家分享一下源代码。-FSM（Finite State Machine） framework
fpga_ctl
- niosII和VHDL的联合应用，VHDL编写基本框架，C++编写niosII应用程序-joint application niosII and VHDL, VHDL prepared a basic framework, C++ to write niosII application
jiao-tong-deng
- 基于fpga的交通灯设计，程序与上一个不同，程序框架有了改变，对比有助于提高。-Fpga-based traffic light design, program, and on a different program framework has changed, help to improve the contrast.
electric-lift-controller
- VHDL编写的电梯控制系统。只有个大概框架程序-The elevator control system written in VHDL. Only a general framework program. ...
fsm
- 有限状态机的一种实现框架，更健壮，更易于表达。-An implementation framework of finite state machines, more robust and easier to express.
TLB
- 用verilog语言实现了快速线性列表的查找，程序实现了一个基本框架，下载下来可以添加新内容-Using verilog language to achieve a fast linear list to find the program implements a basic framework, you can add new content downloaded
cpu_1
- 用verilog设计五级CPU的框架，需要自己另行补充指令，可作为学生作业和训练内容-Five CPU with verilog design framework, needs its own separate supplemental instruction can be used as student assignments and training content
finite-state-machine
- 有限状态机，程序基本框架，需用户自行添加状态转换条件等-finite state machine
FPGA_txt
- 该源码为基于FPGA所开发的TXT文本阅读器，本模块可运用于阅读器开发的实际运用中，并且可用作FPGA开发各类阅读器的模板框架-The source code for the development of FPGA-based TXT text reader, the module can be used in the practical development of the reader, and can be used as FPGA development of various types
ModelCPU
- 包含模型机设计的框架代码 可手动添加其他相关代码完成各种功能设计(The framework code that contains model machine design can be added manually)