搜索资源列表
xcv
- verilog编写的状态机检测00100序列. 实现 input:...011000010010000... output:...000000000100100... 并且 用测试模块来验证状态是否正确工作-verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... a
blocking
- 基于verilog语言的数据选择器，包括数据选择器的测试模块 -verilog language based on the data selector, including data selection for the test module
lq057q3dc02.tar
- lcd测试模块,用VHDL写的,产生彩条信号
uart
- 一个用verilog实现的fpga上的uart接口模块，包括测试模块和实体，并实现了输出接口和状态接口。
i2c_slave
- I2c中通信的从机发送和接收信息的Verilog程序测试模块，用Modelsim仿真通过
DDR2_module_VHDL_test(Rev0.1)
- ddr 2 接口读写测试模块 ddr 2 接口读写测试模块
Verilog--shiyanbaogao
- 有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的. 练习三 利用条件语句实现计数分频时序电路 实验目的： 1. 掌握条件语句在简单时序模块设计中的使用； 2. 学习在Verilog模块中应用计数器； 3. 学习测试模块的编写、综合和不同层次的仿真。 练习四 阻塞赋值与非阻塞赋值的区别 实验目的： 1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别； 2． 了解阻塞赋值与非阻塞赋值的不同使用场合； 3． 学习测试模块的编写、综合和不同层
DDRSDRAMControllerverilogcode
- 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Fron
cpu(FinalWithYS)
- verilog实现的八位CPU，包括乘法、除法以及多种寻址方式。代码中包括测试模块，可以直接在试验箱上运行。-verilog to achieve the eight CPU, including multiplication, division, as well as addressing a variety of ways. Code, including test modules, can be run directly in the chamber.
pci_bridge
- 基于WISHBONE的pci桥实现，包括功能模块和测试模块-Based on the pci bridge WISHBONE implementation, including functional modules and test modules
gen_fifo_usb1
- slaver fifo测试模块，分为三个模块，generate产生数据，然后写如fifo.再传如usbslaver fifo-slaver fifo test module consists of three modules, generate production data, and then write as fifo. re-transmission, such as usbslaver fifo
verilog
- 一些基本器件的实现，包括选择器，计数器，移位寄存器，多位寄存器以及各种测试模块-The realization of some of the basic devices, including the selection, counters, shift registers, a number of registers and a variety of test modules
MUX16
- 基于VerilogHDL的简易的16位以为累加乘法器，包括乘法器模块和测试模块，已经通过仿真测试。-Based on the simple VerilogHDL that the cumulative 16-bit multiplier, including the multiplier module and test module has been tested by simulation.
ram-rom-VerilogHDL
- 利用Verilog编写的各种RAM ROM的代码以及他们的测试模块-Prepared using a variety of RAM ROM Verilog code and their test module
rs232top
- 链接 rcv 和txm的测试模块 验证 接受 和 传输模块功能-Links rcv and txm test module validation capabilities to receive and transmit modules
i2c_module
- i2c 模块，包含测试 和接受传输 外加 测试模块-i2c modules, including additional testing and accept the transfer test module
spi
- spi总线模块和测试模块，接收端的spi模块。-spi bus module and test module, the receiving end of the spi module.
shizhong
- 含有时钟及测试模块，有时分秒年月日周的判定和自动计时跑动功能。-Contains a clock and test modules, month, day and sometimes every second week to determine the timing and automatic running function.
lattice_i2c
- lattice公司的i2c核rd1006 包含testbench测试模块-lattice' s i2c core rd1006 (includes test module testbench
General-memory-VHDL-code-library
- 通用存储器VHDL代码库。fifo,ram寄存器的代码和测试模块。-General-purpose memory VHDL code base. fifo, ram register code and test modules.