搜索资源列表
altera的IP源码
- Altera的IP源码8259，只需打开就能实现-Altera IP source 8259, will be realized only open
kpjsj
- 次源码实现一个扩频接收机系统，用VHDL语言编写，并且有完整得测试程序
若干74HCxxx的Verilog源码。
- 包括：74HC85、74HC138、74HC161、74HC151、74HC373 74HC4017、74HC238、74HC194等器件的Verilog编码实现。为.V文件，也可直接用记事本等打开。
AES加密的VHDL源码
- 用VHDL语言实现的AES加密算法的源代码，已经在硬件上下载运行实现了。
EBCOT Processor 源码
- 硬件实现JPEG2000 EBCOT 编码的源码
GPS去载波verilog实现
- 该源码用verilog实现gps信号的去载波过程
encode_t tlk2201发射接收源码
- tlk2201发射接收源码，8b10b编解码器，实现千兆速率收发。可用于视频光端机接收发射处理串并变换。-tlk2201 transmitting and receiving source, 8b10b codec to achieve gigabit rate transceiver. Optical receiver can be used to transmit video processing strings and transform.
DDR_SDRAM.rar
- DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA,DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
UTOPIA
- utopia接口模块VHDL源码,实现UTOPIA接口功能,可进行UTOPIA接口仿真-utopia interface module VHDL source code to achieve UTOPIA interface functions can be carried out UTOPIA Interface Simulation
add
- 一位全加器源码实现了MAX及其一系列器件实现全加的功能-A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian
fpga_pc
- 该源码实现了XILINX的FPGA(Spartan 3E)与计算机的通信，用到了rs232串口、ps/2键盘接口、lcd液晶，是学习FPGA很好的资料-The source implementation of the XILINX' s FPGA (Spartan 3E) and computer communications, use the rs232 serial port, ps/2 keyboard interface, lcd LCD is good information t
verilog-compiler
- 本文包含了几个关于Verilog的编译器的源码实现，适用于深入学习Verilog的读者-This article contains several Verilog compiler source for in-depth study of Verilog reader
RS232C_vhdl.rar
- RS232C标准的VDDL源码实现，经测试可用，其便于集成到大的系统之中。,The codes of VHDL for RS232C, its useful characteristic can be integrated in a big system.
DW8051_ALL
- DW8051Verilog源码实现 含有说明书 绝对可用-DW8051Verilog source to achieve contain instructions absolutely available
mmuart_latest.tar
- uuart 串口的verilog 源码实现，欢迎下载使用. uart 串口 verilog-uuart serial verilog source implementation, welcome to download
avr_core_latest.tar
- avr cpu verilog 源码实现，欢迎下载使用-avr cpu verilog source implementations are welcome to download
vhdl
- 本文件夹包含了四个代码分别为十进制，六进制，六十进制和交通灯控制器的vhdl源码实现-This folder contains the four codes are decimal, hex, decimal, and six traffic light controller vhdl source implementation
32位CPU IVERILOG源码
- 介绍在FPGA中如何实现32位CPU涉及到额 IVERILOG源码(Describes how to implement 32 bit CPU in FPGA, involving the amount of IVERILOG source code)
DATA_Interleaver
- 这是交织的实现源码 可用于具体的工程实践(This is the interwoven implementation source code that can be used in specific engineering practices)
数字信号处理的FPGA实现(第4版)源码
- 数字信号处理的FPGA实现(第4版)的配套源码，极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)