搜索资源列表
fdpll
- 简单的可配置dpll的VHDL代码。 用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
ddc
- 数字下变频，vhdl代码，包含CIC和HF滤波-vhdl
lbuff_mem
- 延时代码,可以用在ＦＰＧＡ数据流水处理，图象处理，滤波-delay code
t1
- 实现电机M/T法测速的VHDL代码，只要修改cnt值大小即可修改M/T法切换的频率，当小于cnt时为T法，大于时为M法。-Motor M/T method velocimetry of the VHDL code, as long as the modified value of cnt to modify the size of M/T method of frequency switching, when cnt is less than for the T method, for M gr
ADAPTIVEFILTER
- 采用vhdl代码描述自适应滤波器，具有很好的可参考性，和实用性-Vhdl code to describe the use of adaptive filter, can be found with a good nature and usefulness of
shuzhuanglvboqi
- 给出了梳状滤波器的编写代码,用于数字信号处理中的滤波器设计-Gives the comb filter to write code for digital signal processing filter design
EDAFIR
- 采用vhdl代码编写的滤波器仿真，对初学者有一定的帮助。-Vhdl coding using filter simulation, there is some help for beginners.
mid-filter
- mid-filter 中值滤波算法的原理及核心代码 word版-mid-filter median filter and the core principles of the code word version
sift-1.1.2_20101207_win
- 包含高斯滤波和sift的FPGA中VHDL代码，相信对做硬件的各位很有用的-FPGA，sift，VHDL code
key_scan
- 这个是学习FPGA时候自己写的键盘扫描的代码。采用的是边沿检测的方法,并且进行了滤波处理，本人测试仿真成功！-This is when the FPGA write their own learning keyboard scan code. Use is edge detection method, and its filtering processing, I test simulation success!
Code_for_MedianFilter33
- 数值图像处理：中值滤波设计，3*3方形窗，边缘检测的设计代码-Numerical image processing: the median filter design, the design code of 3* 3 square window, edge detection
sfdppllli
- 简单易懂的可配置dpll的VHDL代码。用于时钟恢复后的相位抖动的的滤波有非常好的效果， 而且能参数化配置pll的级数。 已通过测试。 -Straightforward configuration VHDL code dpll. Very good results for the clock recovery phase jitter filtering, and can be parameterized configuration pll series. Has been tested.
infmt
- 攒人品上传多年工作积累代码。主要功能是对视频输入信号的滤波等控制。可以综合。-Save the character to upload the accumulation of many years of working code. The main function is to control video input signal filtering. Can be integrated.
dintlace
- 功能超强的视频信号隔行转逐行的滤波verilog代码，经过fpga验证。-The function of super-interlaced video signal transfer progressive filter Verilog code, after the fpga verification.
AD_DF_DA
- FIR滤波代码，先是AD的控制，后面是滤波的代码，系数通过matlab生成-FIR filter
cic_cq
- 在altera平台用verilog硬件描述语言实现cic抽取滤波，包含完整的工程代码，已经仿真通过，可以直接用于实践-In the Altera platform using Verilog hardware descr iption language CIC decimation filter, contains the complete project code, has been adopted by simulation, can be used directly in practice
cic_cz
- 在altera平台用verilog硬件描述语言实现cic插值滤波，在modelsim软件中仿真通过，包含完整的工程代码，可以直接下载到FPGA中运行-In the Altera platform using Verilog hardware descr iption language CIC interpolation filter, through the simulation in Modelsim software, including the complete project co
Median-implemnt-baseline-drift
- 工程文件中代码是通过中值滤波算法实现基线漂移-Project file code median filtering algorithm by baseline drift
dac_900
- DAC900芯片驱动的Verilog语言描述，亲测可用。另外的是FIR滤波代码和DDS波形发生器的代码。既可单独使用，也可以整合在一起。-DAC900 chips driven Verilog language descr iption, pro-test available. Another is the FIR filter code and DDS waveform generator code. Either used alone or can be integrated.
polyPhaseFilter
- 数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)