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EP1C3_12_9_DDS
- 直接数字式频率合成器(DDS)设计实验(电子设计竞赛赛题) 其它详细资料说明请参考 http://www.kx-soc.com-direct digital frequency synthesis (DDS) experimental design (Electronic Design Contest tournament title) said other details Please refer to prescribed http://www.kx-soc.com
dengjingdu.rar
- 根据第三届（1997年）全国大学生电子设计竞赛题目：简易数字频率计，完全用FPGA芯片做的一个等精度数字频率计。,According to the third (1997) National Undergraduate Electronic Design Contest Topic: simple digital frequency meter, complete with a FPGA chip, such as doing precision digital frequency meter.
WaveformGenerator
- 安徽省首届大学生电子设计竞赛，用VHDL编写的程序任意波形产生器-Anhui first Undergraduate Electronic Design Contest, using VHDL procedures for the preparation of Arbitrary Waveform Generator
VGA_exercise
- 2010北京市大学生电子设计竞赛开发板XILINX-Spatan3E的VGA口练习资料-Undergraduate Electronic Design Contest in Beijing 2010 development board XILINX-Spatan3E the VGA port practice information
danpianjixitongban
- 全国大学生电子设计竞赛单片机最小系统版-内含原理图、系统版等文档和图。-National Undergraduate Electronic Design Contest SCM minimum system version- includes schematics, system version and other documents and plans.
Altera
- “Altera杯”第五届全国研究生电子设计竞赛样板-" Altera Cup" of the Fifth National Graduate Electronic Design Competition model
2011-EDA-1
- 2011全国电子创新设计竞赛培训资料，第一手原创资料-EDA-Electronic Innovate Design
PLD-LOGIC_SPWM
- 电子设计竞赛中获二等奖，在FPGA中实现的两路自然采样SPWM，原理图输入法设计，1024*八位正弦查找表，带FSK和ASK调制功能，频率范围8KHz~12KHz.-Electronic Design Competition second prize in the FPGA to achieve the two natural sampling SPWM, schematic design input, 1024* eight sine look-up table, with FSK and A
SG_FPGA
- 2006年电子设计竞赛二等奖，多功能函数、信号发生器核心器件FPGA内部的原理图，主要模块用VHDL代码描述，包括PLL、相位累加器、波形算法和正弦波查找表，可实现0.005Hz~20MHz的多波形信号产生，频率步进值0.005，输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the devic
3
- 2010电子设计竞赛PicoBlaze FPGA 参考资料-2010 Electronic Design Contest PicoBlaze FPGA Reference
phase
- 2012年江苏省电子设计竞赛，测相位差程序。可分辨相位的超前于滞后，经测试稳定可靠！-Electronic Design Contest in 2012, Jiangsu Province, the phase difference measurement procedures. Distinguished phase ahead of the lag has been tested and is stable and reliable!
RANGEN
- 2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。-2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-seq
DDS
- 基于FPGA完成2001年电子设计竞赛直接数字频率合成器，有FPGA部分、MSP430程序以及相互通信的程序，完成题目全部要求-FPGA-based Electronic Design Competition 2001 complete direct digital frequency synthesizer, there is part of the program FPGA, MSP430 procedures and communicate with each other, to comp
E_2011
- 生成了一个M序列，适用于2011年全国电子设计竞赛的F题(A M sequence is generated that applies to the F question of the 2011 National Electronic Design Competition)