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X-HDL_3.2.55_license
- X-HDL软件是可以智能地实现vhdl<->verilog之间的相互转换的软件，不仅仅是语法转换，而是使用了hdl技术。这是该软件x-hdl3.2.55的license注册补丁，非常难得。
color_converter.tar
- 此代码实现不同图像颜色制式之间的相互转换，如XYZ<->RGB, 不同标准的RGB<->RGB 以及RGB<->YCbCr之间的转换，包内含有matlab仿真代码m文件、VHDL代码.v文件以及modelsim仿真的testbench文件，相信对大家有一定的帮助
X-HDL3.2.52
- vhdl和Verilog HDL相互转换的软件，很难找的一款-vhdl and Verilog HDL mutual conversion software, very difficult to find a
XHDL3Version3·2·37
- vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换-verilog language vhdl language and conversion tools can easily achieve the conversion between two languages
AMI_HDB3
- VHDL实现AMI码和HDB3码之间的相互转换，编译环境为Quartus II 6.1-HDB3 AMI code and VHDL code to achieve conversion between, the build environment for the Quartus II 6.1
PAL-NTSC-transfer-to-CIF
- 本文通过对模拟，数字电视信号技多媒体数字通信传输 ¨孵梗霸艰J公萸中儡格式的基本情况的分橱，提出TPAL制 和NTgC翩两种电视删式s公共中润格式的相互转换聚理， 井就数字税频瞄缘估号处殚所甩曲部分集成电路芯片作F简 要介绍，-In this paper, analog, digital TV signal transmission technology multimedia digital communication difficulties J Pa ¨ hatched ma
four_bit-full-adder
- 四位的全加器，包含8421码与2421码的相互转换，2421码的加法修正-Four of the full adder, including 8421 yards and 2421 yards of the conversion, the addition of amendments to 2421 yards
USB-COM-routines
- 使用CPLD实现的USB通讯与UART通讯相互转换，USB通讯速率可以达到20M 使用专用USB接口芯片cy7c68013芯片-Using CPLD implementation of USB communication and conversion between UART communication, USB communication speed can reach 20M using the dedicated USB interface chip chip cy7c68013
src
- yuv444 与yuv422相互转换verilog语言-yuv444 to yuv422
data_switch
- verilog 实现15bit数据与176bit数据间的相互转换，可根据此代码作一定的修改，可以实现其他位宽数据的转换-verilog to achieve mutual conversion between 15bit data with 176bit data can make certain changes based on this code, you can achieve the conversion of other bit-wide data
jsq
- 基于FPGA的计算器，可以实现加减乘除运算功能，由于时间问题，浮点运算未能实现，其中的二进制与BCD码相互转换的模块可以使用-FPGA-based calculator, arithmetic calculation function can be achieved, due to time issues, floating-point operations failed to achieve, including binary and BCD code conversion modules t
verilog
- 用verilog设计的寄存器，储存器，锁存器，译码器以及在其中用到的八位串联并联间的相互转换。-Verilog design registers, memory, lock latch decoder and the use of eight series parallel conversion
vhdl-convert-verilog
- vhdl与verilog相互转换的工具，在xp条件下可以破解成功，win7下只能用demo模式-vhdl and verilog conversion tools in xp successful break conditions, can only be used under win7 demo mode
color_converter_latest.tar
- 彩色空间转换的VHDL源代码，可以实现CIE XYZ<->RGB， different RGB<->RGB和RGB<->YCbCr之间的相互转换，使用3x3矩阵模板(a color transform tasks such as CIE XYZ<->RGB, different RGB<->RGB and RGB<->YCbCr operations. The main part of color conversions f