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Triggersignalaccuratedataacquisitionsystemdesignde
- 在一些系统中，经常用到对触发信号延时一段时 间后，再对某些目标信号进行采集，通常这段延时要求 非常精确，还要做到范围可调，一般这种延时的最小时 间单位小于100ns。如果选用普通微控制器，延时系统的操作界面比较容易实现，但是靠软件延时得到结果的准确性较低。考虑到芯片功能、开发环境以及接口方便等问题，最终选用一片常用的AlteraSVCPLD EPM7128SLC3411]作为系统的核心控制部分，来实现 信号延时、输人设定、运行显示的功能。应用Veril- o苦2〕语言，在
FPGA_DE2_MUSIC
- 基于FPGA的乐曲硬件演奏模块设计，利用硬件描述语言设计符合技术指标的乐曲硬件发生模块，建立实验模型，通过电路仿真和下载硬件测试，在DE2 EDA实验平台上验证其功能-FPGA-based music performance modular design of hardware, using hardware descr iption language designed to meet specifications of the piece of hardware modules occurs,
FFT_verilog
- verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
rs232
- fpga的串口读写程序，经硬件测试成功，波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
hbf
- 半带插值滤波器设计、综合、仿真和硬件测试-Half-band interpolation filter design, synthesis, simulation and hardware test
tlv5636
- 音频DA tlv5636的接口程序 经过硬件测试的成功 学习状态机对器件编程的经典-DA tlv5636 audio through the interface program to test the success of hardware 。state machine to study the classic programming device
fft_rtl
- rtl实现的fft变换，经硬件测试其功能与altera的fftip核相近-fft transform based on rtl design
VHDlclock
- 数字秒表的VHDL课程设计 通过硬件测试 精确到ms 最大可计时为24小时 -Digital stopwatch curriculum design through the VHDL hardware testing is accurate to ms maximum time of 24 hours
direct_moto
- 基于FPGA的直流电机驱动，有32级速度选择，正反转和使能端。在硬件测试通过，效果良好-FPGA-based DC motor drive, there are 32 speed options, positive inversion, and enable end. On the hardware test results were very good
dds
- dds信号发生器，硬件测试过，效果良好。文件包含整个fpga开发过程产生的所有文件-dds signal generator, the hardware tested to good effect. File contains the entire fpga development process of all documents generated
vga5
- VGA彩条发生器设计，可实现8条横、竖彩条和多彩棋盘格的显示。经过硬件测试，-VGA Color Bar Generator designed to achieve the eight horizontal, vertical color bars and colorful checkerboard display. After the hardware test,
fpu100_latest.tar
- 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
EDA3add
- 序列信号发生器与检测器设计：用状态机设计实现串行序列检测器的设计，先设计（可用原理图输入法）序列信号发生器产生序列：0111010011011010；再设计检测器，若检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。-Sequence signal generator and detector design: The Design and Implementation of a serial sequence of state machine design of
MC8051_IPcore_lab
- 一个关于8051Core 在FPGA上的应用的文档，通过一个简单C51 程序对51Core 进行硬件测试-One on 8051Core in the FPGA application on the document, C51 through a simple hardware test program 51Core
EDA1
- 掌握Quartus II 的VHDL 文本设计的全过程； （2）熟练和掌握EDA设计流程；熟悉简单组合电路的设计，掌握系统仿真，学会分析硬件测试结果。 （3）学习PH-1V型实验装置上发光二极管和按键的使用方法。 -Quartus II VHDL text grasp of the whole process of design (2) skilled and master the EDA design flow familiar with the simple combinat
EDA3
- 实验目的 1．学习一般有限状态机的设计； 2．实现串行序列的设计。 二、设计要求 1． 先设计0111010011011010序列信号发生器； 2． 再设计一个序列信号检测器，若系统检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。 -Purpose of the experiment 1. Learning the general design of finite state machine 2. Serial sequence de
ad0809VHDL
- ADC0809控制程序，用VHDL语言实现，简单实用，已通过硬件测试-ADC0809 control procedures, using VHDL language, simple and practical, has passed the hardware test
cuiEDA
- 用VHDL语言写的脉冲宽度测量仪，本人课程设计题目，已经通过硬件测试-VHDL language to write the pulse width measuring instrument, a design course, I have been tested by the hardware
SystemVerilog
- SystemVerilog 是一个硬件测试语言。可以搭建测试平台。本书有很多的测试用例。并且会告知你如何使用该语言。-SystemVerilog for Verification A Guide to Learning the Testbench Language Features Second Edition
FPGA-SRAM_Test
- 利用FPGA实现SDRAM的读写操作，通过硬件测试。-FPGA implementation using SDRAM to read and write operation, hardware testing.