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frequency_counter_2(successful)(top-down design).r
- 小巧的频率计数器，VHDL源代码和仿真文件具全，直接从管工程文件拷贝过来。绝对可用。-compact frequency counters, VHDL source code and simulation with all documents directly from the control engineering documents copied. Absolutely available.
isatoi2c
- 本程序实现的是ISA转I2C的功能,绝对可用-this program is the ISA I2C transfer function can be absolute
redandyellow
- 交通灯，十字路口红绿灯的VHDL程序，绝对可用-traffic lights, traffic lights crossroads VHDL procedures, absolutely available
LED
- 用VHDL语言实现的八个开关控制八个LED灯的亮灭，本程序经过实验箱认证，绝对可用。-VHDL language used to achieve the eight switch control eight bright LED lights out, the procedure experimental boxes after certification, available absolutely.
ds18b20
- 这是基于NIOS II的 DS18B20 的源码，绝对可用本人已经调试成功，希望对大家有-It s a DS18B20 code for nios ii.
Spartan3E_ADC
- 专门针对xilinx 的spartan3e开发板上的ADC转化的编程，绝对可用，仿真通过-Xilinx the spartan3e specific development board ADC conversion program, absolutely free, simulation by
[VGA_Sopc
- VGA的一个例子,绝对可用,在工程上已经应用了-a good example, is the vga in using
SIN_WAVE_DAC0832
- 输出正弦波 用rom da832绝对可用-Absolute sine wave output available with rom da832
VHDLPWM
- fpga输出pwm的vhdl程序，已经过开发板试验，绝对可用,包括所有文件。-fpga vhdl output pwm' s program has been developed plate test, absolutely free.
31241213verilog_uart_NO
- FPGA串口通讯例程，经我修改绝对可用； 默认48M,9600-8-1/2，如果时钟不同只需修改时钟分频数即可。-The FPGA serial interface communication by the modified routine, absolute can be used The default 48 M, 9600-8-1/2, if the clock different modify it only clock points frequency can.
p2s_code
- 并行输入，串行输出模块，输入的位宽在1--16位可变，包括测试平台，自己写的，绝对可用，已经通过modelsim仿真。-Parallel input, serial output module, the input bit-width of 1- 16-bit variable, including the test platform, write your own, absolutely free, Has passed the modelsim simulation.
SEG_Dynamic
- 用vhdl实现四位数码管的程序，可用于计时等功能，绝对可用-well,my english is so poor that i can not translate it
Meter-taxi
- 我自己写的在STC（AT）89C51上用的出租车计价器程序，绝对可用的，放心下载吧-I wrote in the STC (AT) on the 89 C51 with the meter taxi program, absolute available, feel free to download it
sdram_mdl
- SDRAM的FPGA 工程。用Verilog编写。器件型号为K4S641632，经过实验板验证，绝对可用。-SDRAM FPGA project. Written in Verilog. Device model K4S641632, after the experimental board, absolutely available.
verilogiic1121
- I2C总线的FPGA工程，Verilog编写。是测试过的程序，绝对可用。-I2C bus of the FPGA project, Verilog prepared. Program is tested, absolutely available.
ps2verilog
- PS2接口的FPGA工程，经过测试，绝对可用。-PS2 port of the FPGA project, after testing, is absolutely available.
uartverilog
- 串口的FPGA工程，经过测试，绝对可用。-Serial port of the FPGA project, tested, and absolutely available.
verilogvga
- VGA接口的FPGA工程，Verilog编写，经过测试，绝对可用。-VGA interface of the FPGA project, Verilog prepared, tested, and absolutely available.
15_tlc5620dac
- DA的FPGA开发工程，DA型号为：TLC5620，经过本人测试，绝对可用-FPGA development project of the DA, DA Model: TLC5620, after I tested, the absolute available
DW8051_ALL
- DW8051Verilog源码实现 含有说明书 绝对可用-DW8051Verilog source to achieve contain instructions absolutely available