搜索资源列表
数字频率计实验报告
- 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter,
traffic
- 计算机系统设计课程实验，交通灯的vhd代码。-Computer systems design course experiment, traffic lights vhd code.
VHDL
- VHDL和数字电路设计课程实验指导，内容丰富-VHDL and digital circuit design course experiment guide, rich in content
EDA
- 课程实验，VHDL语言实现半加器全加器，频率计等，共四个-eda
Stopwatch
- 这个设计是电子科技大学集成电路综合课程实验的项目，主要内容是跑表-This design is the University of Electronic Science and Technology Experiment IC integrated curriculum project, the main contents of stopwatch
experiment6
- VHDL课程实验6，数控分频器的设计。对应不同的输入信号，预置数（初始计数值）设定不同的值，计数器以此预置数为初始状态进行不同模值的计数，当计数器的状态全为1时，计数器输出溢出信号。用计数器的溢出信号作为输出信号或输出信号的控制值，使输出信号的频率受控于输入的预置数-VHDL course experiment 6, NC Divider. Corresponding to different input signals, the set value (initial count) to set
PipelineCPU
- 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Nios_II_Exercises
- 嵌入式可编程片上系统设计SOPC课程实验资料，包括一个教Nios II使用的doc格式英文教程和对应工程文件。工程已解压，请自动忽略教程的第一步。-Embedded programmable system on chip design SOPC course of experimental data, including a Nios II used to teach English tutorial doc format and the corresponding project file.
shuzishizhong
- 可实现数字时钟功能 用于EDA课程实验 有计时，闹钟，还可自行设置调整时间功能-Digital clock function can be used with EDA time course experiment, alarm clock, can set their own time adjustment function
jishuqi
- EDA课程实验计数器 16位基本计数器 并可简易级联为48位 96位计数器-EDA course experiment the basic counter and 16-bit counter cascade of simple 48-bit counter 96
AM2901
- 计算机系统设计课程实验，AM2901的vhd代码-Computer systems design course experiment, AM2901 vhd code
decoder_38
- 计算机系统设计课程实验，38译码器的vhd代码-Computer systems design course experiment, 38 decoder vhd code
code
- 可编程器件课程实验相关代码。硬件描述语言中不同的描述，会综合出不同的硬件电路。-The programmable device curriculum experiments relevant code. The descr iption of the hardware descr iption language, will be integrated hardware circuit.
zhong
- 数字钟，实现整点报时以及校时功能，烟大数字逻辑课程实验。-Digital clock, realize the whole point timekeeping and school function, smoke large digital logic course experiment.
jingsai
- 微机原理课程实验应用，竞赛抢答器的设计，文本档-Microcomputer Principle Course Laboratory applications, Contest Responder design, text files
miaobiao
- FPGA课程实验，基于xinlix实验平台的秒表程序实现，下载到实验板上，测试通过。-FPGA experiment, the experiment platform based on xinlix stopwatch program implementation, download to experiment, the test pass.
shumaguan
- FPGA课程实验代码，基于xinlix实验开发平台的数码管显示学号完整程序，下载到实验板，测试通过。-FPGA experiment courses code, based on xinlix experimental platform of digital tube display full program student id, download to experiment board, the test pass.
jp
- led灯按顺序显示，EDA课程实验,verilog语言(EDA experiment with Verilog language)
cpu2
- 这是在vivado平台上编写的多功能流水线cpu的实现，是我们课程实验的大作业(This is the implementation of the multi-functional pipelined CPU written on the vivado platform. It's a big job for our course experiment.)
实验考试系统与复习题代码
- 微机原理课程实验课期末考试 操作考试可以使用的万能平台(The universal system platform used for the microcomputer principle course operation examination)