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riscpu
- 一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.-a 32 Microprocessor verilog achieve pulse generation sources, used five lines and cache technology.
32bit_RISC_CPU
- 32 risc cpu的参考设计，内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
RISC
- 32 bit RISC Processor with 3 stage pipeline
ALU
- verilog硬件仿真，实现32-bit RISC微处理器的算数逻辑单仿真元(ALU),实现加减运算、逻辑运算、移位运算。仿真级别为RTL级。-verilog hardware simulation, to achieve 32-bit RISC microprocessor arithmetic logic one simulation element (ALU), to achieve addition and subtraction operations, logic operations
A-RISC-Design
- RISC设计：MIPS指令集控制器核，详细介绍一款32位risc-cpu。-A RISC Design:Synthesis of the MIPS Processor Core
cpu
- 用verilog实现的一个32位RISC处理器，能够实现简单的移位、加法等基本操作。-Verilog implementation with a 32-bit RISC processor to achieve a simple shift, addition and other basic operations.
tiny64_latest.tar
- Descr iption Tiny64 A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles. The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also differnet word sizes. Due simpli
risc-processor
- 32 bit risc processor
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p
ug230.pdf
- The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications. The board highlights these features: • Spartan-3E FPGA specific fe
Amber_ARM-compatible_core_latest.tar
- The Amber processor core is an ARM-compatible 32-bit RISC processor. The Amber core is fully compatible with the ARM ® v2a instruction set architecture (ISA) and is therefore supported by the GNU toolset. This older version of the ARM instr
risc32_datapath
- Risc - 32 Bit Datapath Only
32-bIT-RISC-DOC-a4
- it is 32 bit risc processor code in vhdl
32-bit-RISC
- 基于MIPS指令集的32位RISC处理器逻辑设计的论文，讲的非常详细适合初学者学习。-32-bit RISC processor logic based on MIPS instruction set design paper, speak very detailed is suitable for beginners to learn.
Chapter4
- MIPS is a reduced instruction set computer (RISC) instruction set architecture (ISA)[1]:A-1[2]:19 developed by MIPS Technologies (formerly MIPS Computer Systems). The early MIPS architectures were 32-bit, with 64-bit versions added later.