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AES
- 利用verilog HDL实现的AES算法，在密码芯片加解密中显示出了突出的优越性-The reference-AES.V which has been uploaded is particularly useful for researchers who are dedicated to the password-chip researching.
AESzuihou
- 在赛灵思软件ISE上实现的ＡＥＳ加解密算法，并且在ＭＯＤＥＬＳＩＭ上仿真。希望对你有所帮助-The Xilinx software ISE AES encryption and decryption algorithms, and simulation MODELSIM on. I hope for your help
AES
- AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。-AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification.
各种密码算法的FPGA实现情况
- 各种密码算法的FPGA实现情况 1.AES算法FPGA实现分析 2.DES加密算法的高速FPGA实现 3.RSA加解密运算的FPGA硬件实现研究(FPGA implementation of various cryptographic algorithms)