搜索资源列表
AES加密的VHDL源码
- 用VHDL语言实现的AES加密算法的源代码，已经在硬件上下载运行实现了。
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
CC2430
- CC2430基础实验源代码，帮助读者快速认知CC2430芯片 ││sch_CC2430ZDK.pdf ││ │├─1.LED │├─2.LCD │├─3.Clock模式 │├─4.External中断 │├─5.Timer中断 │├─6.Stop观看 │├─7.ADC │├─8.Temp传感器 │├─9.Joystick │├─10.UART - 液晶 │├─11.DMA │├─12.ADC_Series │├─13.Flash写作
base-on-FPGA-AES-addkey-design
- 介绍了用FPGA实现AES算法所用的开发工具，开发语言和所选用的芯片，及AES算法的硬件实现方式。着重阐述了AES算法FPGA实现的总体设计框图，并副有部分源代码- introduce design tool,language and core of AES which base on FPGA,and AES hardware design.
AES_verilog
- 对AES算法加密解密的Verilog源代码，可以实现其128位和256位明文密文之间的转换。-AES algorithm for encryption and decryption of Verilog source code, can achieve the conversion of its 128 and 256 between the plaintext ciphertext.
AES
- AES的加密解密verilog全部源代码-AES encryption and decryption verilog full source code
20161227_sf
- AES加密算法中的列混合模块的FPGA实现源代码，采用Verillog语言，在软件Quartus II上综合-AES encryption algorithm in the FPGA column hybrid module implementation source code, using language Verillog integrated in the Quartus II software