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dds_ise7.1_su
- 用Verilog语言实现信号发生器，包括AM，FM,PM，ASK,PSK,FSK调制。-using Verilog language signal generator, including AM, FM, PM, ASK, PSK, FSK modulation.
AM
- AM信号的调制解调DSP算法，包括原理和应用-AM
fpga
- 基于FPGA的信号调制，可产生正弦波，并进行ASK调制和AM调制-FPGA-based signal modulation, can produce sine wave, and the ASK modulation and AM modulation
if-receiver
- 中频数字接收机设计与实现 对中频数字接收机方案的可行性作了分析，并通过系统仿真工具SystemView对A／D，数字下变频(DDC)及AM、FM等调制信号的软件解调作了仿真。-Design and implementation of a digital intermediate frequency receiver
dds
- dds数字信号发生器，实现1/4rom存储，正弦，余弦，三角波，锯齿波产生，AM调制-the dds digital signal generator, achieve 1/4rom store, generate sine, cosine, triangle wave, sawtooth, AM modulation
am
- 基于FPGA的用verilog语言写的，改程序可产生不同调制系数和不同频率的AM波，长按按键切换调制度25 、50 、75 和短按按键切换调制信号频率1k、1.5k、2k、2.5k.-Based on the FPGA using verilog language, change the program can produce different coefficients and different frequency modulated AM wave, long press the butt
DSB
- FPGA中实现的DSB的AM调制，带Modelsim仿真，实际测试通过：载波频率，信号频率以及调制度可调。-The FPGA implemented in the DSB AM modulation with Modelsim simulation, the actual test: the carrier frequency, and modulation signal frequency is adjustable.
Lab4
- 该实验室会议的目的是要实现一个可配置的FM-AM数字调制器的数据通路。它是由一个CIC内插滤波器及可配置的FM-AM块。调制器信号以48kHz被取样，并且由CIC内插滤波器的装置内插高达96MHz的。在FM-AM配置块适用于96 MHz的时钟-The aim of this laboratory session is to implement the data-path of a configurable FM-AM digital modulator. It is composed of
AM调制解调
- 基于Artix-7 FPGA的AM调制解调代码，从AD读入信号后，进行AM调制，并解调输出（将代码分成两个工程就是AM的调制和解调），其中解调用到的数字滤波采用MATLAB设计(The AM modulation and demodulation code based on artix-7 FPGA, after reading the signal from AD, carries out AM modulation, and demodulates the output (the code