用verilog编写的fir滤波器程序，开发环境可以用ise quartus或active hdl等-verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl

有源电力滤波器，用于实现无功治理与谐波补偿，精度很高-Active power filter for reactive power control and harmonic compensation, high accuracy