用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.

CAN总线的FPGA实现源代码,Verilog语言实现-CAN Bus FPGA source code