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1024_FFT
- 1024点FFT快速傅立叶变换，包含说明文档和VHDL源代码，16位输入/输出，带DMA功能，xilinx的ip-1024-point FFT fast Fourier transform, and includes documentation, VHDL source code, 16 input / output, with DMA function, the ip xilinx
adma
- Wishbone dma ip core
dma_ahb_latest.tar
- this shows the ip code for dma controller of amba ahb in vhdl.
sdcard_mass_storage_controller_latest.tar
- 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
VGA_Controller
- 这个文件简直太好了，是个ip，费了好大的力气弄好的，可以挂在avalon总线上，用dma的方式将数据弄处理放在vga上进行显示。-This file is simply too good to be a ip, take a great effort things right, you can hang in the avalon bus, with the way the data get dma handle on the vga on the display.
dma_0
- SOPC系统编译的DMA的Verilog代码-DMA IP core in SOPC
wb_dma_latest.tar
- 这是一个简单IP核的DMA桥，他有两个WISHBONE接口，该平台可实现在两个相同或不同接口之间DMA数据的搬运。-This is a simple DMA/Bridge IP core. It has two WISHBONE interface. It can perform DMA transfers between the two interfaces or on the same interfaces.
A8237
- Altera Quartus Megacore of A8237 (DMA Controller). Published by Altera for free after the IP Megacore portfolio has changed.
xapp1052
- ML605开发版 生成IP核的时候选择250MHZ pcie2.0 X4 5Gb/s 其他参考PDF文档。(When the ML605 development version generates the IP kernel, select 250MHZ pcie2.0 X4 5Gb/s Other reference PDF documents.)
AXI-HP-ZYNQ
- 用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can
eetop.cn_kc705
- Xilinx PCIE IP核的应用例程，带DMA，有V6和KC705的应用(Xilinx PCIE IP DMA example)