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fir滤波器设计
- 详细介绍了，给予FPGA设计fir滤波器，里面有详尽的VHDL代码。
fir_hdl.rar
- 一个 FIR 滤波器的 verilog 实现， 与 matlab 产生的 reference code 相互验证。,Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
fir.rar
- fir滤波器，Verilog语言写的，容易看懂,fir filter, Verilog language written in easy to understand
fir_16
- fir滤波器-verilog，基于verilog的fir滤波器源码-fir filter-verilog, the fir filter based on the Verilog source code
fir
- 比较简单的16位fir滤波器，16阶，Verilog编写-Simple 16-bit fir filter, 16 bands, Verilog prepared
FIR_VHDL
- FIR滤波器的VHDL代码,可以修改冲击函数的值-FIR filter VHDL code can modify the impact of the value function
FIR
- 用verilog设计的FIR滤波器。滤波器需要很快的处理速度，所以采用了wallace树算法，超前进位加法器-The FIR filter is designed with verilog. To improve the process speed, wallace tree and fast-carrylook-aheadarithmetic were used.
FIR
- 基于FPGA的FIR滤波器设计思想，里面有很好的算法供大家参考-FPGA-based FIR filter design ideas, there are very good for your reference algorithm
vhdl
- FIR滤波器的性能参数 设计一个滤波器最基本的就是性能参数的,决定着滤波器的实际功能.比如阶数,截至频率。 本文滤波器设计参数 ①输入,输出数据宽度10位 ②阶数为4阶的线性相位FIR滤波器， ③类型:带通 -FIR filter performance parameters The design of a filter is the most basic performance parameters, determines the actual filter fu
verilog.DA.FIR..
- 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
fir
- 利用VHDL语言，设计了一个11阶的FIR滤波器。简单易懂-The use of VHDL language, designed a 11-order FIR filter. Easy to understand. .
FIR
- FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。-FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.
fir-c2h
- 基于fpga的fir滤波器的设计 非常好，谢谢大家分享-fir filter design base on fpga it is very good
firfilter
- FIR滤波器：自定滤波器的类型（低通，高通或带通）、设计指标（通带截止频率、通带波纹、阻带截止频率、阻带衰减） 1、根据指标选择合适的窗函数，用窗口设计法设计符合指标的FIR滤波器；并验证其性能是否满足预定指标。 -FIR filters: Custom filter types (low pass, high pass or band-pass), design specifications (passband cutoff frequency, passband ripple, st
fir
- Verilog编的fir滤波器，可以自己输入参数序列，产生滤波波形-Verilog compiled fir filter, input parameters can be their own sequence, resulting in filtered waveforms
fir
- 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information i
FPGA-FIR
- FIR滤波器，算法，采用VHDL编程语言，算法比较简单，希望对大家有所帮助。-FIR filter algorithm, using VHDL programming language, the algorithm is simple, we want to help.
fir
- fir 滤波器的程序文件和测试文件，仿真数据和matlab仿真数据进行过比对，matlab采用fdatool生成的低通滤波器，采样率为24兆，通带2.5M，截止频率为5M(FIR filter program files and test files, simulation data and MATLAB simulation data have been compared, Matlab using FDATool generated low-pass filter, sampling rat
FIR滤波器
- STM32f407 DSP库应用 FIR滤波器 用示波器测试PA8，可以测出1Khz的正弦波。如果不是，修改PWM参数，使其正好为1Khz.(STM32f407 DSP library uses FIR filter Oscilloscope PA8 test, you can measure the sine wave of 1Khz. If not, modify the PWM parameter to make it exactly 1Khz.)
FIR
- 采用加法树设计8位乘法器，具有流水线结构7阶FIR滤波器，输入序列信号字长4位表示，并且是无符号数。(An adder tree is used to design the 8 bit multiplier, which has a pipelined 7 order FIR filter. The input sequence signal is 4 bits, and it is an unsigned number.)