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基于FPGA的数字频率计
- 基于FPGA的数字频率计
FPGA.rar
- FPGA，vhdl语言的学习资料； FPGA的简单设计 dds的设计,FPGA, vhdl language learning materials FPGA design of a simple design dds
dds
- verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
dds
- 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
FPGA-VHDL-DDS
- 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
dds-design
- fpga实现dds，实现任意波形输出信，设计代码verilog-dds fpga realization
dds
- 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
dds
- fpga利用dds原理，产生正弦波，简单实用，成本低-fpga using dds principle, have a sine wave
DDS
- 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
DDS
- 同时用verilog 语言编写dds原代码用于生成正余弦波，并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
dds
- 基于FPGA的DDS波形信号发生器，功能强大，代码规范，值得学习-FPGA-based DDS waveform signal generator, powerful, code specifications, it is worth learning
DDS
- 本代码在fpga中实现了dds，程序有三个按键：一个控制产生的波形（正弦波或方波），另两个控制频率增加或降低。程序附有注释，并在signaltap中仿真成功。-The code is implemented in fpga a dds, program has three buttons: a control generated waveform (sine or square wave), the other two control the frequency increase or decr
FPGA-VHDL-DDS
- 这是基于FPGA的直接数字频率合成器的程序，是VHDL语言-This is based on FPGA for direct digital frequency synthesizer program that is VHDL language
DDS
- 毕业设计，基于FPGA的DDS设计与实现模块-FPGA DDS
DDS
- 基于FPGA的DDS直接信号合成器，基于Altera CYcloneII系列-DDS direct FPGA-based signal synthesis, based on Altera CYcloneII Series
DDS-in-Verilog
- Verilog编写基于FPGA的DDS实现，内含源代码，希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
DDS
- 基于FPGA的DDS正弦信号设计，文件中有源代码(Design of DDS based on FPGA)
DDS
- 用verilog语言，在fpga上实现dds信号发生器，并在vga上显示出来(Verilog realizes DDS Signal Generator)
DDS
- 基于FPGA的DDS信号发生器，可产生频率可调的正弦波(DDS signal generator based on FPGA)
Signal
- 基于FPGA的DDS相位累加器，连接至存有波形数据的rom后再接至DA可以输出对应的波形(abcdefghijklmnopqrstuvwxyz)