搜索资源列表
rs232
- 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
UCOS_II-transplant
- uCOS_II 在NiosII处理器上的移植过程以及全部源代码-uCOS_II NiosII processor in the transplant process and the full source code
arm9_fpga2_verilog
- ARM9的开发源代码，全套，很难得。 现全部共享。-ARM9 development of source code, a full set, it is difficult to get. Are all shared.
rel_08_done
- 修改自OpenCores的黑白棋游戏代码。采用VGA输出显示，PS2键盘（W、A、S、D、回车）输入控制，实现AI，LED灯指示是否游戏结束，VGA显示频率25MHz，系统频率50MHz，经过Cyclone IV芯片EP4CE115F29C7N的板级调试，实现全部功能，文件夹下有rtl源代码，管脚定义pin文件，和可以直接进行JTAG烧写和E2PROM烧写的pof和sof文件，-Modified from OpenCores Othello game code. Using the VGA ou
VHDL_display
- VHDL实现的示波器-完整的文档和源代码，可在fpga实现-VHDL realization Oscilloscopes- Full documentation and source code, can achieve in the FPGA
seven
- 这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器，通过独特的3次映射一位全加器的方法从而实现七人表决器的功能，与网络上任何其他的七人表决器源码决无雷同。-This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full a
F_adder
- 这个源程序是关于全加器的，又需要的同学可以借鉴一下 -This source code is on the full adder, and also the needs of students can learn from you
add
- 一位全加器源码实现了MAX及其一系列器件实现全加的功能-A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian
FIFO
- 完整的FIFO完整源代码，通过仿真 完整的FIFO完整源代码，通过仿真 -Complete FIFO full source code, through the simulation of the complete FIFO full source code, through the simulation of
VerilogHdlPracticeAndSystemDesign
- 本RAR包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。-The RAR includes " Verilog-HDL Practice and Application of system design," a book full of examples, all passed validation. Ch
Adder4
- 源码，内容是用VHDL语言编写的四位全加器-Source code, using VHDL language of the four full-adder
fulladde
- 全加器源代码，VHDL语言编写，有需要的参考参考-Full adder source code, VHDL language, the need to reference information
subtractor
- Verilog source code for full subtractor module build with predefined nor gates.
active-hdl-vhdl-code
- this vhdl source code for multiplexer,half adder,full adder,counter etc. for using in ACTIVE HDL and other vlsi softwares.-this is vhdl source code for multiplexer,half adder,full adder,counter etc. for using in ACTIVE HDL and other vlsi softwares.
PIC_project
- PIC 16F84A SOURCE code full 100 working.all modules compiled in one file.-PIC 16F84A SOURCE code full 100 working.all modules compiled in one file.
FPGASDRAMverilog
- 一个基于Xilinx FPGA的DDRSDRAM的Verilog控制代码，使用的FPGA为Virtex完整源代码。-A Xilinx FPGA-based control DDRSDRAM the Verilog code for the Virtex FPGA using the full source code.
8051-and-AD1674
- C8051 and AD1674 ,全部源代码，直接仿真使用-On C8051 and the AD1674, full source code, the direct simulation use
yi-wei-er-jin-zhi-quan-jia-qi
- 一位二进制全加器的源代码及详细WORD文档，maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-A binary full source code and detailed documentation WORD, maxplus software running, pin has been configured, EP1K30TC144-3
AES
- AES的加密解密verilog全部源代码-AES encryption and decryption verilog full source code
mips-cpu-master
- MIPS Implementation in Verilog. Full source code!