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  1. histogram4

    0下载:
  2. 利用matlab和modelsim完成了用直方图均衡化处理灰色图片的前仿真,有处理前后图片的对比,verilog语言编写,但到用实时处理还差很远-Completed using matlab and modelsim deal with the gray image histogram equalization before the simulation, a comparison of before and after pictures, verilog language, but with
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-12
    • 文件大小:19930397
    • 提供者:杨兔艳
  1. histogram-equalization-verilog

    0下载:
  2. 直方图均衡的Verilog实现 从Matlab读出图像为image.txt文件,经过Modelsim读入TXT文件进行直方图均衡处理,将输出结果再读出为image_he.txt文件,然后在Matlab观察直方图均衡增强效果。-The histogram equalization Verilog read from Matlab the image image.txt file after the Modelsim read into the TXT file, histogram equaliz
  3. 所属分类:VHDL编程

    • 发布日期:2014-01-16
    • 文件大小:2062
    • 提供者:杨光
  1. eup

    0下载:
  2. It is the HDL and MATLAB code for image processing in Modelsim.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-24
    • 文件大小:29417
    • 提供者:M
  1. image-rotation

    0下载:
  2. 基于FPGA的system generator的图像旋转处理,利用system generator的图像旋转处理程序。本程序是基于system generator下的matlab运行。-FPGA-based image processing system generator rotation, the use of image rotation system generator handler. This procedure is based on matlab run under the sy
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:158706
    • 提供者:wyj
  1. isjtc

    0下载:
  2. Use serial programming examples matlab GUI implementation, Independent component analysis for image processing, Realize image watermarking, de-noising, plus noise and other functions.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-26
    • 文件大小:4096
    • 提供者:fyqdwg
  1. xjrsb

    0下载:
  2. Based on matlab GUI interface design, Complete class-based image processing, contains all of the source code, auto image, Related impulse response analysis algorithm and inspection.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-25
    • 文件大小:12288
    • 提供者:jienenfui
  1. tang_ip61

    0下载:
  2. The received signal is given eye and BER simulation systems, In the MATLAB image texture feature, Contains a common array signal processing algorithm.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-24
    • 文件大小:8192
    • 提供者:nengqeisui
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