搜索资源列表
oc_mkjpeg
- Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design.
JPEG2000
- jpeg 2000 encoder complete document
vhdl-JPEG-enc
- JPEG Encoder,Here is a quite detailed low level design document for the Core: Low Level Design Document
fpga-jpeg
- 基于FPGA的JPEG图像压缩，实现JPEG图像的实时压缩-FPGA JPEG compress
JPEG-Encoder
- Buffer encoder for creating JPEG encoder IP core
buffer_comp.vhd
- Describe the TABLE FOR ENCODER TO DESIGN jpeg -Describe the TABLE FOR ENCODER TO DESIGN jpeg
q_rom.xcp
- dESIGN THE ROM ENCODER FOR jpeg
JPEG_Encode_verilog
- JPEG Encoder，JEPEG编码的Verilog代码-JPEG Encoder, JEPEG coded Verilog code
verilog-encoder
- JPEG的編碼器 使用VERILOG以硬體實現 也使用MODEL模擬驗證-JPEG encoder using the VERILOG hardware implementation is also used to simulate authentication MODEL
based-DE2-jpeg-encoder-design
- 使用基于Altera公司的DE2平台进行JPEG 编码器的设计与实现，硕士论文-Altera' s DE2-based platform for JPEG Encoder Design and Implementation, Master' s thesis
Embedded-JPEG-Codec-Library
- An open source JPEG codec library optimized for embedded system, including both encoder and decoder. Compact, optimized for specific hardware, easy to be ported to various embedded OS, ESL tools like Handel-C, multi-processor systems and FPGA.
fbas_encoder_latest.tar
- FPGA BASELINE ENCODER (jpeg mpeg)
JPEG
- JPEG Encoder Verilog Source Code
jpeg_encoder
- JPEG 编码器IP核，用verilog语言编写，不支持二级采样。-JPEG Encoder IP Core,The core is written in Verilog and is designed to be portable to any target device. This core does not perform subsampling- the resulting JPEG image will have 4:4:4 subsampling
jpegencoder
- jpeg encoder in vhdl including modules MAC, Wavelet encoder, filter bank, image to text converter
fpga-jpeg
- fpga 实现 jpeg 编码，已在altera 公司fpga上测试通过。-jpeg encoder ,has been tested in altera FPGA