搜索资源列表
mxuliematlab
- m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
color_converter.tar
- 此代码实现不同图像颜色制式之间的相互转换，如XYZ<->RGB, 不同标准的RGB<->RGB 以及RGB<->YCbCr之间的转换，包内含有matlab仿真代码m文件、VHDL代码.v文件以及modelsim仿真的testbench文件，相信对大家有一定的帮助
ug_lpm_rom.rar
- quartus rom的生成 运用matlab生成.mif或.hex文件 载入rom表,quartus rom the use of matlab generated generation. mif or. hex file loading rom Table
verilog_m
- 用verilog生成的m序列，包含四个.v的文件-verilog m sequence
code
- modelsim下的60进制计数器源码和测试激励文件-modelsim M counter 60 under the source file and test incentives
mvhdl
- 此文件中包含m序列发生器详细的vhdl源码，欢迎各位下载-it is a file of m porducor based on vhdl
m
- m序列生成文件，带有我自己写的仿真，结果在modelsim6.0f中生成正确。-m sequence generation file, written with my own simulation results generated in the modelsim6.0f correct.
SD_Controller_Verilog
- 该程序包是SD卡/MMC卡控制器SDC的verilog语言包，它包括以下4部分：RTL源代码，测试平台，软件仿真文件，说明文件。-This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help
randomization
- m序列码生成文件-M code generation file................
lab_2
- VHDL 实现M序列发生器 附带测试与限定文件-M-sequence generator VHDL incidental test with limited file
M=15generator
- 模15序列发生器，Verilog HDL语言描述，包含文件说明和波形截图-mod15 generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
shuzixinhao
- 使用verilog编程，实现m序列发生，m转化为曼彻斯特编码。已经过仿真，拥有vt文件。-Use verilog programming, the realization of m sequence, m into Manchester coding. Simulation, has been with vt.
m
- 本设计实现了一个12级m序列发生器，包含源文件及其测试文件。-This design has realized a level 12 m sequence generator, and the test file contains the source file.
m_sequence_mod
- 伪随机序列，m序列发生器，可灵活配置抽头文件，已经仿真通过-m SEQ MODULE